FIFO Structure

Figure 5.13 shows the implementation of the FIFO. Every FIFO in our design has five stages. According to Muller pipeline, the utilization of the 4-phase dual rail pipeline is 50%. So the FIFO packs three data/packets at most. The detail design for each C-latch is shown in figure 5.14.

The transistor-level C-element is shown has been shown in chapter 2.1.2. An alternatively implementation of C-element in gate-level is shown in figure 5.15.

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Figure 5.14：C-latch in FIFO

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B

C

Reset

Figure 5.15：The C-element with reset

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Chapter 6 Simulation

6.1 Testing Environment

ModelSim 6.0 is used to verify the correctness of the functionality. Figure 5.16 shows the waveform of the functionality of the read request phase. Figure 5.17 shows the waveform of the read response phase. Figure 5.18 and figure 5.19 show the write request phase and write response phase respectively.

Figure 6.1：The waveform of the read request phase

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Figure 6.2：The waveform of the read response phase

Figure 6.3：The waveform of the write request phase

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Figure 6.4：The waveform of the write response phase

6.2 Area Report

To evaluate the design of the ANIP interfaces and Resource Network Interface, we use the synthesis tool from Synposys under TSMC 0.13um library. Table 6.1 shows the area information of each module in our design. The Network Wrapper consists of the slave interface and the resource network interface, and the RNI consists of the request path and the response path. Moreover, the response path of RNI is consists of the packet buffer and other modules.

The area of slave interface is three times larger than the master interface. Because of the number of FIFO of the slave interface is four, which is more than the number of FIFO in of the master interface. Each FIFO consists of five 32-bit C-latches. The area of a FIFO is about 6654μm², which is a large proportion of the ANIP interface.

The area of the packet buffer is 177157.6μm², which is 66.3% of the network wrapper.

The line size of the packet buffer is 39 bits, and there are 64 entries in the packet buffer, and

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the packet table has four entries with 18bits line size. There are at most four groups of packets which are from different resources storing in the packet buffer, due to the limit of the entries in the packet table. The number of buffer lines of the packet buffer can be parameterized by the interface designer. Table 6.2 shows the area information of basic element.

Module Cell Area(μm²) %

Master Interface 15507.4 -

Network Wrapper 266820.9 100

1.Slave Interface 43497.5 16.3

2.Resource Network Interface 223323.4 83.7

a. Request Path 32204.7 12.0

b. Response Path 191118.7 71.6

Packet Buffer 177157.6 66.3 Table 6.1: The Area of each module

Element Area(um²)

C-element 20.3

32-bit C-latch 1330.8

DeMUX 889.4

Dual Rail OR 217.2 Table 6.2: The Area of basic element

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Chapter 7 Conclusion

We proposed asynchronous network-on-chip protocol and implementation of the resource network interface in this thesis. The ANIP makes the network interconnection details transparent to the IP blocks. The IP designers can easily design the MPSoC system regardless of the way to transmit the packets of NoC. The RNI decouples communication and computing, bridging the command between ANIP interface and router. We can utilize ANIP to integrate an asynchronous two way VLIW processor with the RNI in the future, building whole asynchronous MPSoC system.

There still have some points that can be improved in our implementation. The cost of dual rail circuits is too high to be commercialized. It may mix with bundle data to deduce the cost. Additionally, the cost of our implementation is still very high. We may use other way to implement the ANIP interface. For example, the FIFO of the ANIP interface can be optimized by way of replacing the C-element with registers.

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References

[1] J. Sparsø and S. Furber, Principles Of Asynchronous Circuit Design A Systems Perspective, Kluwer Academic Publishers, London, 2001.

[2] S. Hauck, “Asynchronous design methodologies: an overview,” Proceedings of the IEEE, Vol. 83, Issue 1, Jan. 1995, pp.69-93

[3] A. Jantsch, J. Soininen, M. Forsell, L. Zheng, S. Kumar, M. Millberg, and J.

Oberg, “Networks on Chip,” Workshop at the European Solid State Circuits Conference, Sep. 2001.

[4] S. Kumar, A. Jantsch, 2002. “A network-on-chip architecture and design methodology”. Proceedings of the Computer Society Annual Symposium on VLSI (ISVLSI). IEEE Computer Society, 117-124

[5] F. Gebali, H. El-Miligi, M. W. El-Kharashi, Networks-On-Chips: Theory and practice, Taylor & Francis Group, LLC, 2009

[6] Lee SE, Bahn JH, Yang YS, Bagherzadeh N, “A generic network interface architecture for a networked processor array (NePA)”. In: ARCS; 2008. pp.

247–60.

[7] S. Yoo, G. Nicolescu, D. Lyonnard, A. Baghdadi, A. A. Jerraya, “A Generic Wrapper Architecture for Multi-Processor SoC Cosimulation and Design,” Int.

Symposium on HW/SW Codesign (CODES) 2001.

[8] Bainbridge, W.J., “Asynchronous System-on-Chip Interconnect,” PhD Thesis, University of Manchester, 2000.

[9] C. C. Tsai, “Asynchronous Bi-direction Interconnection Network Implementation using Torus Topology”, Master Thesis, National Chiao Tung University, 2009.

[10] ARM: AXI protocol, http://www.arm.com

[11] Open Core Protocol international partnership, http://www.ocpip.org

[12] David Duarte, Vijaykrishman Narayanan and Mary Jane Irwin, “Impact of Technology Scaling in the Clock System Power”, IEEE International Computer Society Annual Symposium on VLSI, 2002

[13] N. C. Paver, “The Design and Implementation of an Asynchronous Microprocessor”, PhD Thesis, University of Manchester, 1994.

[14] J.D. Garside, W.J. Bainbridge, “AMULET3i-an Asynchronous System-on-Chip” In Third International Symposium on Advanced Research in Asynchronous Circuits and Systems, ASYNC’97. Department of Computer Science, The University of Manchester, April 1999.

[15] W.J. Bainbridge, S.B Furber, “Asynchronous Macrocell Interconnect using MARBLE” Proc. Async 1998, San Diego, April 1998 pp. 122-132