The decoder is divided into 5 submodule, i.e., the ACSU, the TBU, the state machine unit (State), the memory and memory control unit (MemCtl), and the frame control unit (FramCtl). Figure 4.9 (a) shows the input and output signal waveforms for a sample run. Figure 4.9 (b) shows some internal signal waveforms. From the function simulation, we obtain the Viterbi decoder outputs compare with convolution encode input data and the result like the MATLAB simulation result. Extract the timing information from place& route tool (Xilinx-Project Navigator), we run the gate level simulation again and obtain the same result as the function simulation. Based on Xilinx Vitrtex-II type FPGA place reports, we found that the critical path is 6ns which is less than 8ns (125MHz). The sampling rate for the WLAN system is 20 MHz and we use the trace back rate by three times. It turns out that the minimum clock rate must be 60MHz.
Prime Power provides the power analysis result shown in Figure 4.8. This figure shows the power consumption behavior when one frame of data is passed through the Viterbi decoder. The average power consumption is listed in Table 4-1. From this table, we can see that the memory access plays the most important role in low power Viterbi decoder design.
Module name average power consumption(%) PMGen(ACS) 21
TB (Decoder) 15 State 0.5 MemCtl 62 FrameCtl 1.5
Table 4.1 Viterbi decoder power consumption distribution
Figure 4.8 Prime power shows Viterbi decoder power consumption
Figure 4.9 (a) Viterbi decoder input and output signal waveform
We perform power analysis for the general design and our low-power design.
The power consumption in digital CMOS circuits is expressed as
P = IstandbyVdd + IleakageVdd + Ishort-circuitVdd + αClVdd× Vdd × fclk (4.6)
where Istandby is the DC current drawn continuously from the Vdd to ground, Ileakage is the leakage current primarily determined by the fabrication technology, and Ishort-circuit
is the current due to the DC path between the supply rails during output transitions.
These three terms correspond to the circuit-level power issue and we do not discuss these topics here. The last term, Cl is the load capacitance, α is a factor depending on switching activity, and fclk denoted the clock frequency.
Table 4-2 lists the power consumption comparison. As we can see, the main power saving for our design comes from the reduction of the memory access frequency. During idle periods, we use “chip enable” to turn off the memory. The
Figure 4.9 (b) Viterbi decoder internal signal waveform
Module name
General design power consumption
Low power design power consumption
Enhance rate
PMGen (ACS) 0.21 mw 0.21 mw 0%
Decoder(TB) 0.15 mw 0.16 mw -1%
State and FrameCtl 0.02 mw 0.02 mw 0%
MemCtl 0.62 mw 0.41 mw 31%
Top(total) 1.00mw 0.80 mw 20%
Table 4.2 Power analysis
Figure 4.10 Prime power shows Viterbi decoder power distribution
Chapter 5 Conclusion
In this thesis, we focus on the low-cost WLAN Viterbi decoder design.
Specifically, we consider the IEEE802.11a system. We proposed a hard decision weighting scheme to enhance the conventional hard-decision Viterbi decoder. The performance enhancement can be as high as 2dB. However, the computational
complexity is still low. This scheme may be useful for some IA applications in which the performance requirement is not stringent. Besides, we also study the receiver diversity scheme and analyze the system performance with 2, 3, 4 receiver antennas.
We have shown that the diversity combining performed inside the Viterbi decoder is better than that performed outside. Finally, we use a trace back prediction method that can reduce the memory access frequency. This approach can effectively reduce the power consumption. Simulations show that the power consumption can be reduced 20%. We then implement the Viterbi decoder using a FPGA design flow.
The Viterbi decoder has been studied for a log time and found applications in many areas. However, it implementation cost is still high compared to other
operations. This is particular true when the receiver diversity is introduced. To obtain higher performance, the BMU and the ACSU will become more complicated. How to keep the high performance while reduce the complexity is a topic for further research.
References
[1] VLSI Digital Signal Processing Systems Design and Implementation
[2] Suk-Jin Jung, Myeong-Hwan Lee and Hyung-Jin Choi,“A New Survivor memory Management Method inViterbi Decoders:Trace-Delete Method and Its
Implementation”,IEEE pp3284-3286
[3] Dae-Il Oh and Sun.-Young. Hwang,”Design of a Viterbi decoder with low power using minimum-transition trace-back scheme”, IEEE Electronics Letters,
vol.32,no. 24, pp. 2189-2199, Nov. 1996.
[4] G.Geygin and P.G Gulak, “Architectural tradeoffs for Survivor Sequence
Memory Management in Viterbi Decoders”, IEEE Trans. Commun., vol.41, no.
3, pp. 425-429, Mar. 1993
[5] C.B.Shung, P.H.Siegel, G.Ungerboeck, and H.K. Thapar,”VLSI Architecutres for Metric Normalization in the Viterbi Algorithm”, SUPERCOMM/ICC, Atlanta, GA, USA, vol.4, pp.1723-1728, Arp. 1990.
[6] G.Feygin, P.G.Gulak, and F. Pollara. “Survivor sequence memory management in Viterbi decoders. In Proc. 3rd Workshop on ECC, pages 72-90, San Jose, CA, Sept 1989.
[7] IEEE Std. 802.11a-1999, Wireless LAN Medium Access Control and Physical Layer specifications: High-speed physical layer in the 5GHz band
[9] A.P. Hekstra, “ An Alternative to Metric Rescaling in Viterbi Decoders”, IEEE Trans. Commun., vol. 37, no.
[10] Lacroix, D., Castelain, D. “ A study of OFDM parameters for high data rate radio LANs”, IEEE VTC, vol.2, pp.1075-1079,2000.
[11] A. J. Viterbi, “Convolutional Codes and Their Performance in Communication Systems”, IEEE Trans. Commun., vol. COM-19, pp. 751-772, Oct. 1971 [12] R.M. Orndorf et al. Viterbi Decoder VLSI integrated circuit for Bit error
Correctin. Rockwell International, Anaheim, California 92803, December 1981 [13] C.B.Shung , implementation Issues for the Design of a Rate 8/10 Trellis Code for Partial Response Channels. In Third IBM Workshop on ECC, San Jose,
California, November 1989.
[14] G.C. Clark and J.B. Cain. Error Correction Coding for Digital Communications, page262. Plenum Press, 1981
[15] C.M. Rader. Memory Management in a Viterbi Algorithm. IEEE Transactions
on communications, 29:1399-1401, September 1981.
[16] Ana Garcia Armado, et al, “Parameter Optimization and Simulated Performance of a DVB-T Digital Television Broadcasting System”, IEEE Trans. on
Broadcasting, Vol.44, No.1 March, pp.131 –138, 1998
[17]M.R.G. Butler, S. Armour, “Viterbi Decoding Strategies for 5 GHZ Wireless LAN Systems” IEEE 2001
[18] O.Collins and F. Pollara, “Memory management in traceback Viterbi decoders”
TDA prog. Rep. 42-99, Jet Prop. Lab., Pasadena, CA, November1989.
[19] A. P. Hekstra. An alternative to metric rescaling in Viterbi decoders. IEEE Trans.
Communications, 37(11):1220-1222, November 1989.
[20] C. B. Shung, Gottfrried Ungerboeck, H. K. Thapar, “VLSI Architecutres for Metric Normalization in the Viterbi Algorithm”, IEEE International Conference wol.4, 1999,pp. 1723-1728