Future Work

For further more research, two aspects are worth to be developed. One of them is a fully digital power management system with dynamic frequency scaling. The architecture of the fully digital power management is shown in Figure 6.1. An all

digital phase-lock-loop (ADPLL) and the Adaptive voltage control system are combined together. The ADPLL divides the reference frequency (Fref) by N. After the adaptive voltage control system defined the predicted performance and the corresponding regulated voltage, the predicted frequency (Fpredict) is feedback to the ADPLL. At last, the ADPLL multiplies the predicted frequency by N. In this way, the lock time of the control system can be reduced since the reference frequency is divided first. Additionally, the frequency scaling can be made by the ADPLL.

Figure 6.1 Fully Digital Power Management System

Another one is Inverse Discrete Cosine Transform design. IDCT is often used in digital signal processing, even more frequently than DCT does. The IDCT design is simple since the operation is almost the same as the DCT, the only difference is the coefficient matrix. The IDCT operation is described by the equation 6.1.

0 7 0

According to the IDCT coefficient matrix, the CSHM architecture still works except the coefficients changed.

Bibliography

[1] N. Chabini, I. Chabini, E.M. Aboulhamid, Y. Savaria, “Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Page(s):346 – 351, Volume 22, Issue 3, March 2003.

[2] C. Yeh, M.-C.Chang, “Gate-level voltage scaling for low-power design using multiple supply voltages,” IEEE Proceedings Circuits, Devices and Systems, Page(s):334 – 339, Volume 146, Issue 6, Dec. 1999.

[3] A. Chandrakasan, S. Sheng, R. Brodersen, “Low-Power CMOS Digital Design”, IEEE Journal of Solid-State Circuits, 27(4), Apr. 1992.

[4] T. Mahnke, S. Panenka, M. Embacher, W. Stechele, W. Hoeld, “Efficiency of dual supply voltage logic synthesis for low power in consideration of varying delay constraint strictness,” 2002. 9th International Conference on Electronics, Circuits and Systems, Page(s):701 - 704, Volume 2, 15-18 Sept. 2002.

[5] K. Usami, M. Igarashi, “Low-power design methodology and applications utilizing dual supply voltages,” Proceedings of the ASP-DAC 2000. Asia and South Pacific Design Automation Conference, 2000, Page(s):123 – 128 , 25-28 Jan. 2000.

[6] D. Liu and C. Svensson, “Trading Speed for Low Power by Choice of Supply and Threshold Voltages”, IEEE Journal of Solid-State Circuits, 28(1), Jan. 1993.

[7] M. Meijer, F. Pessolano, J. Pineda de Gyvez, “Technology Exploration for Adaptive Power and Frequency Scaling in 90nm CMOS,” Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004.

ISLPED '04, Page(s):14 – 19, 2004.

[8] Jaeha Kim, M.A. Horowitz, “An efficient digital sliding controller for adaptive power-supply regulation,” IEEE Journal of Solid-State Circuits, Page(s):639 – 647, Volume 37, Issue 5, May 2002.

[9] A. Dancy, A. Chandrakasan, “Techniques for aggressive supply voltage scaling

and efficient regulation [CMOS digital circuits],” Proceedings of the IEEE 1997 Custom Integrated Circuits Conference, 1997, Page(s):579 – 586, 5-8 May 1997.

[10] A. Stratakos, S. Sanders, and R.W. Brodersen, “A Low-voltage CMOS DC-DC Converter for Portable Battery-operated Systems”, Proceedings of the Twenty-Fifth IEEE Power Electronics Specialist Conference, pp. 619-626, June 1994.

[11] Min Jiang, Yuan Luo, Yiling Fu, Bing Yang, Baoying Zhao, Xin-an Wang, Shimin Sheng, Tianyi Zhang, “A low power 1D-DCT processor for MPEG-targeted real-time applications,” ISCIT 2004. IEEE International Symposium on Communications and Information Technology, 2004, Page(s):682 – 687, Volume 2, 26-29 Oct. 2004.

[12] Yeong-Kang Lai, and Han-Jen Hsu, “A cost-effective 2-D discrete cosine transform processor with reconfigurable datapath,” Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03, Pg.II-492 - II-495, Vol.2, 25-28 May 2003.

[13] J.Park and K.Roy, ” A low power reconfigurable DCT architecture to trade off image quality for computational complexity,” Processing, 2004. Proceedings.

(ICASSP '04). IEEE International Conference on Acoustics, Speech, and Signal, Pg.V - 17-20, Vol.5, 17-21 May 2004.

[14] Jongsun Park, Soonkeon Kwon and Kaushik Roy, “Low power reconfigurable DCT design based on sharing multiplication.” IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings. , pp. III/3116- III/3119, Vol. 3, 2002.

[15] Yi-Jong Yeh, Sy-Yen Kuo, Jing-Yang Jou, “Converter-free multiple-voltage scaling techniques for low-power CMOS digital design,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Page(s):172 – 176, Volume 20, Issue 1, Jan. 2001.

[16] “A system level memory power optimization technique using multiple supply and threshold voltages,” T. Ishihara, K. Asada, Proceedings of the ASP-DAC

2001. Asia and South Pacific Design Automation Conference, 2001, Page(s):456 – 461, 30 Jan.-2 Feb. 2001.

[17] Yi-Jong Yeh, Sy-Yen Kuo, “An optimization-based low-power voltage scaling technique using multiple supply voltages,” The 2001 IEEE International Symposium onCircuits and Systems, 2001. ISCAS 2001, Page(s):535 - 538, Volume 5, 6-9 May 2001.

[18] J.T. Kao, M. Miyazaki, A.R. Chandrakasan, “A 175-MV multiply-accumulate unit using an adaptive supply voltage and body bias architecture,” IEEE Journal of Solid-State Circuits, Page(s):1545 – 1554, Volume 37, Issue 11, Nov. 2002.

[19] M. Elgebaly, M. Sachdev, “Efficient adaptive voltage scaling system through on-chip critical path emulation,” ISLPED '04. Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Page(s):375 – 380, 9-11 Aug. 2004.

[20] S. Dhar, D. Maksimovic, “Low-power digital filtering using multiple voltage distribution and adaptive voltage scaling,” ISLPED '00. Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, Page(s):207 – 209 ,2000.

[21] M. Meijer, J.P. de Gyvez, R. Otten, “On-chip digital power supply control for system-on-chip applications,” ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, Page(s):311 – 314, 8-10 Aug. 2005.

[22] S. Dhar, D. Maksimovic, “Switching regulator with dynamically adjustable supply voltage for low power VLSI,” IECON '01. The 27th Annual Conference of the IEEE Industrial Electronics Society, 2001, Page(s):1874 - 1879, Volume 3, 29 Nov.-2 Dec. 2001.

[23] Shoei-Chuen Lin and Ching-Chih Tsai, “Adaptive voltage regulation of PWM buck DC-DC converters using backstepping sliding mode control,” Proceedings of the 2004 IEEE International Conference on Control Applications, 2004, Page(s):1382 – 1387, Volume 2, 2-4 Sept. 2004.

[24] Martin Yeung-Kei Chui, Wing-Hung Ki, Chi-Ying Tsui, “An integrated digital controller for DC-DC switching converter with dual-band switching,” 2003 Symposium on VLSI Circuits, 2003. Digest of Technical Papers, Page(s):45 – 48, 12-14 June 2003.

[25] Hong Mao, J. Abu-Qahouq, Shiguo Luo, I. Batarseh, “Zero-voltage-switching half-bridge DC-DC converter with modified PWM control method,” IEEE Transactions on Power Electronics, Page(s):947 – 958, Volume 19, Issue 4, July 2004.

[26] Kyeounsoo Kim, P.A. Beerel, “A high-performance low-power asynchronous matrix-vector multiplier for discrete cosine transform,” The First IEEE Asia Pacific Conference on ASICs, 1999. AP-ASIC '99, Page(s):135 – 138, 23-25 Aug 1999.

[27] Min Jiang, Yuan Luo, Yiling Fu, Bing Yang, Baoying Zhao, Xin-an Wang, Shimin Sheng, Tianyi Zhang, “A low power 1D-DCT processor for MPEG-targeted real-time applications,” IEEE International Symposium on Communications and Information Technology, 2004. ISCIT 2004, Page(s):682 – 687, Volume 2, 26-29 Oct 2004.