Chapter 5 Conclusions and Future Work
5.2 Future Work
1. The goal of low leakage current：
We must try to research the other new process and the other gas plasma treatment to reduce the defects and suppress the leakage current in HfAlO thin film further.
2. More potential interfacial layer investigation：
The quality of the interfacial layer still must be improved. Moreover, in order to improve the quality at high-k/Si-substrate interafce, other more potential interfacial layers maybe can be investigated in the future. For example：HfSiON.
3. Devices fabrication with the above results：
The optimum condition will be used to the structures of our MOS device in the future.
Table
Table 1-1 The time of intel corporation found a solution for high-k and metal gate to keep continuation of Moor’s Law
Table 1-2: Material requirements of high-k dielectrics
Table 1-3 Comparison of relevant properties for various high- k candidates [32].
aCalculated by Robertson.
bMono.=monoclinic.
cTetrag.=tetragonal.
Table 2-1 Comparison of deposition techniques: Sputter, ALCVD, and MOCVD [53].
Figure-chapter 1
Figure 1-1 Illustration of Moore’s law: number of transistors integrated in the different generations of Intel’s microprocessors vs. the production year of these circuits.
Figure 1-2 Trend of device scaling: Transistor physical gate length will reach
~ 15nm before end of this decade and ~ 10nm early next decade.
Fig. 1-3 With the marching of technology nodes, gate dielectric has to be shrunk and five silicon atoms thick of gate dielectric is predicted for 2012.[2]
Fig. 1-4 Measured and simulated Ig-Vgcharacteristics under inversion condition for nMOSFETs. The dotted line indicates the 1A/cm2 limit for the leakage current. [3]
Fig. 1-5 Conduction mechanism in oxide for the MOS structure.
Figure 1-6 (a) Energy band chart of NMOS device (b) The influence of poly-Si depletion for capacitance density.
Fig. 1-7 High-k+ metal gate transistors provide significant performance increase and leakage current reduction , ensuring continuation of moor’s law.
Figure 1-8 Power consumption and gate leakage current density comparing to the potential reduction in leakage current by an alternative dielectric exhibiting the same equivalent oxide thickness [5].
(a) Schottky Emission (SE)
(b) Frenkel-Poole Emission (FP)
(c) Fowler-Nordheim Tunneling (F-N)
Figure 1-9 (a) Schottky Emission (SE) (b) Frenkel-Poole Emission (FP) (c)Fowler-Nordheim Tunneling (F-N) current transport mechanism.
Figure 1-10 schemes of important regions in gate stack of a field effect transistor
Figure-chapter 2
Fig. 2-1 Schematic diagram of MOCVD system structure.
Fig. 2-2 The ICP plasma system that was used in this experiment.
Fig.2-3 (1)Si substrate RCA clean (2)6 nm HfAlO was deposited on the sub-Si by MOCVD.
Fig.2-4 (1) PDA by RTA (2) Plasma treatment (3) PNA by RTA
Fig.2-5 40 nm Ti was deposited on the HfAlO layer by dual e-gun evaporation system .
Fig.2-6 400 nm Al was deposited on the Ti layer as top electrode by thermal evaporation coater.
Fig.2-7 Undefined Al was removed by wet etching .
Fig.2-8 Undefined Ti was removed by wet etching (1%HF).
Fig.2-9 Al was deposited on the back side of sub-Si as bottom electrode by thermal evaporation coater.
Fig. 2-10 MOS diode capacitance structure
Fig. 2-11 The energy band plot and electric charges distribution of MOS diode capacitance under bias voltage.
Fig. 2-12 The capacitance-voltage curve of three different conditions
Figure-chapter 3
Fig.3-1 The capacitance-voltage (C-V) characteristics of HfAlO gate dielectrics treated with N2 plasma treatment for different process time.
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0
Fig.3-2 The capacitance-voltage (C-V) characteristics of HfAlO gate dielectrics treated with NH3 plasma treatment for different process time.
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0
Fig.3-3 The capacitance-voltage (C-V) characteristics of HfAlO gate dielectrics treated with N2Oplasma treatment for different process time.
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0
Fig.3-4 The capacitance-voltage (C-V) characteristics of HfAlO gate dielectrics treated with N2 plasma treatment, NH3 plasma treatment and N2O plasma treatment all for 30 sec.
-2.0 -1.5 -1.0 -0.5 0.0
Fig. 3-5 The J-V characteristics of p-type HfAlOcapacitors treated by N2 plasma with different process time from 0 V to -2 V.
-2.0 -1.5 -1.0 -0.5 0.0
Fig. 3-6 The J-V characteristics of p-type HfAlOcapacitors treated by NH3 plasma with different process time from 0 V to -2 V.
-2.0 -1.5 -1.0 -0.5 0.0
Fig. 3-7 The J-V characteristics of p-type HfAlOcapacitors treated by N2Oplasma with different process time from 0 V to -2 V.
-2.0 -1.5 -1.0 -0.5 0.0
Fig. 3-8 The J-V characteristics of HfAlOgate dielectrics treated with N2 plasma treatment, NH3 plasma treatment and N2Oplasma treatment all for 30 sec.
Figure-chapter 4
Fig. 4-1 The hysteresis of p-type HfAlOgate dielectrics treated without PDA, plasma treatment, PNA.
Fig. 4-2 The hysteresis of p-type HfAlOgate dielectrics treated with PDA, N2 plasma treatment, PNA.
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0
Fig. 4-3 The hysteresis of p-type HfAlO gate dielectrics treated with PDA, NH3 plasma treatment, PNA.
Fig. 4-4 The hysteresis of p-type HfAlO gate dielectrics treated with PDA, N2O plasma treatment, PNA.
-2.0 -1.5 -1.0 -0.5 0.0
SILC after CVS -3V for 180sec
Voltage(V) 8000C-60sec+N2-10sec+6000C-60sec+SILC 8000 8000C-60sec+N2-60sec+6000C-60sec+SILC 8000
Fig. 4-5 The SILC curve of p-type HfAlOgate dielectrics treated with N2 plasma treatment for different process time.
-2.0 -1.5 -1.0 -0.5 0.0
SILC after CVS -3V for 180sec
Voltage(V) Gate Leakage ( A/cm2 )
Fig. 4-6 The SILC curve of p-type HfAlOgate dielectrics treated with NH3 plasma treatment for different process time.
-2.0 -1.5 -1.0 -0.5 0.0
SILC after CVS -3V for 180sec
Voltage(V) Gate Leakage ( A/cm2 )
Fig. 4-7 The SILC curve of p-type HfAlOgate dielectrics treated with N2Oplasma treatment for different process time.
0 20 40 60 80 100 120 140 160 180
Gate Leakag e shift ( A/cm
2)
Fig. 4-8 The gate current shift of p-type HfAlOgate dielectrics treated with N2 plasma treatment for different process time as a function of stress time during Vg = -3 V CVS stress.
0 20 40 60 80 100 120 140 160 180
Fig. 4-9 The gate current shift of p-type HfAlOgate dielectrics treated with NH3 plasma treatment for different process time as a function of stress time during Vg = -3 V CVS stress.
Fig. 4-10 The gate current shift of p-type HfAlOgate dielectrics treated with N2O plasma treatment for different process time as a function of stress time during Vg = -3 V CVS stress.
0 20 40 60 80 100 120 140 160 180
Gate L eakag e shi ft ( A/ cm
2)
Fig. 4-11 The CVS compare of HfAlO gate dielectrics treated with N2 plasma treatment , NH3 plasma treatment and N2Oplasma treatment all for 30 sec.
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0
Fig. 4-12 The capacitance-voltage (C-V) characteristics of HfAlOgate dielectrics treated with PDA, N2, NH3, N2O plasma treatment all for 30 sec, PNA plus 950℃ 30 sec.
-2.0 -1.5 -1.0 -0.5 0.0
Fig. 4-13 The J-V characteristics of HfAlOgate dielectrics treated with PDA, N2, NH3, N2O plasma treatment all for 30 sec, PNA plus 950℃ 30 sec.
Fig. 4-14 The J-V characteristics of HfAlOgate dielectrics treated with N2 plasma treatment , NH3 plasma treatment and N2Oplasma treatment all for 30 sec and then measured at 25℃ and 125℃.
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簡歷
姓 名：蘇明紳 性 別：男
出生日期：民國 65 年 11 月 1 日 出 生 地：台灣省彰化縣
住 址：彰化縣秀水鄉埔崙村民生街607巷11號 學 歷：
國立彰化高中
(民國81 年9 月~民國84 年6 月) 國立中興大學土木工程學系 (民國86 年9 月~民國90 年6 月)
國立交通大學電機學院微電子奈米科技產業研發碩士班 (民國95 年3 月~民國97 年1 月)
碩士論文：電漿處理氧化鋁鉿閘極介電層之研究
The study of plasma treatment on HfAlO gate dielectrics