Future Work

As discussed in the above, the processing speed of Viterbi decoder is the bottleneck in our IEEE 802.16a FED procedure. However, we have adopted the most efficient algorithm we know of and it is hard to further accelerate it by algorithm fine tuning. One way to implement and accelerate the Viterbi decoder is to design VLSI logic and parallelize its operations. So, the FED scheme may be accelerated by implementing the Viterbi decoder using the FPGA with the help of DSP. The DSP platform we use in this project contains an Xilinx FPGA. It may worth to try.

There are also other issues in the AMR codec implementation. It is not yet implemented for the analog input and output although they are included on the DSP

baseboard we use. Reading and writing files are the primary I/O for our present implementation. It would be more useful in practice to process real-time input speech or audio using the microphone and the speaker. However, we are limited by the time and not yet to test and use the I/O port. This can be another subject to explore.

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