DSP Program Flow for Viterbi Decoder

The interface of the Viterbi decoder implementation is shown in Fig. 6.7 and is similar to that of the RS decoder except for the text edit box, which is the coding mode.

The program execution flow is also similar to that of the RS decoder, shown as Fig. 6.6, but no code mode is needed to be judged in the Viterbi decoder.

Figure 6.7: the Interface of the Viterbi Decoder Implementation

6.3.3 Performance Analysis

In this section, we present the execution time of our implementation for the RS decoder and Viterbi decoder of the IEEE 802.16a wireless communication standard.

The execution time and the code size of our proposed implementation system is shown in Table 6.9.

Implemented

Decoder Name Code Size Processing Rate (Kbytes/sec)

Improvement Percentage (%)

the Original RS

Decoder 17,137,575 58.80 N/A

Improved RS

Decoder 17,139,055 176.40 96.44

Viterbi 17,120,975 17.42 N/A

Table 6.9: Profile of our Implementation for RS Decoder and Viterbi Decoder

It is observed that the code sizes of the both decoder implementations are almost the same because the largest part included in the final code is the overhead of the transfer mechanism, the functions, and the constants that have been ready by the library.

The improved RS decoder is up to 176.4 Kbytes/sec of the processing rate, and its improvement gain is up to 96.44% compared to the Lee RS decoder without the file-level optimization. The processing rate of the Viterbi decoder is about 17.42 Kbytes/sec. To accelerate the Viterbi decoder, it seems better to design the logic for parallelize its operation than to execute it sequentially on the DSP platform. Moreover, the algorithm of the Viterbi decoder is almost fixed, and we are only able to measure its efficiency on the DSP platform.

Chapter 7

Conclusions and Future Works

7.1 Conclusions

The speech coding approach taken by AMR is a way to adjust the speech and channel coding rate to the channel condition without losing too much quality. The Reed-Solomon codec in IEEE 802.16a provides several coding rates and error capabilities for the wireless communication. However the multiple speech coding modes and the additional channel coding for reducing channel errors increase the complexity of the implementation on the hardware. However, the technique of VLSI and architecture design advances rapidly at the present time. It gives us the opportunity to implement complicated algorithms on hardware. In this thesis, the AMR speech codec is implemented on the DSP platform, which is used mainly for multimedia coding purposes. And so is the Reed-Solomon decoder, which is used wildly because of its high capability of correcting both random and burst errors.

In the previous chapters, we first focus on the AMR speech codec. We profile the C program provided by 3GPP and find that most functions mainly consist of the function call of arithmetic operations. Hence it is an effective way to reduce much execution time by accelerating the arithmetic operations. We also use the TI DSP intrinsics, which are efficient instructions supported by the C64x DSP to take the advantage of the DSP architecture, to accelerate the AMR codec. It has been improved

up to 68.88% for the encoder and 66.12% for the decoder when the compiler-level optimization is also enabled. Finally, we implement the accelerated program on the DSP platform, and its speed is up to 14.05 ms/frame for the encoder and 2.43 ms/frame for the decoder. The measured time includes the data transfer and still meets the real time.

The other topic in this thesis is the Reed-Solomon decoder in IEEE 802.16a. The conventional decoding algorithm is described and treated as the original one for further improvement. The original decoder is first profiled. And then it is accelerated in the syndrome computation and chien search modules, which are two most time consuming procedures. We reduce their complexity and simplify their structure for the software pipeline. It is improved up to 97.79% in the syndrome computation and 73.72% in the chien search. The improved Reed-Solomon decoder is also implemented on the DSP platform. Its processing speed is up to 176.4 Kbytes/sec and is 96.44% faster than the original one. The Viterbi decoder is also implemented to complete the FED scheme in our IEEE 802.16a project. Its processing rate of DSP implementation is 17.42 Kbytes/sec. The final version of both the Reed-Solomon decoder and the Viterbi decoder in IEEE 802.16a reaches our goal of real time for the AMR speech coding.

7.2 Future Works

As discussed in the above, the processing speed of Viterbi decoder is the bottleneck in our IEEE 802.16a FED procedure. However, we have adopted the most efficient algorithm we know of and it is hard to further accelerate it by algorithm fine tuning. One way to implement and accelerate the Viterbi decoder is to design VLSI logic and parallelize its operations. So, the FED scheme may be accelerated by implementing the Viterbi decoder using the FPGA with the help of DSP. The DSP platform we use in this project contains an Xilinx FPGA. It may worth to try.

There are also other issues in the AMR codec implementation. It is not yet implemented for the analog input and output although they are included on the DSP

baseboard we use. Reading and writing files are the primary I/O for our present implementation. It would be more useful in practice to process real-time input speech or audio using the microphone and the speaker. However, we are limited by the time and not yet to test and use the I/O port. This can be another subject to explore.

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