Gate Tracking Circuit

The signals “bias” and “biasp” generated by dynamic bias circuitry are fed to gate tracking circuit for gate protection. The gate tracking circuitry not only transmits logic levels to “PAD” but also protects output buffer stage not to be damaged by high voltage input (VDDHVP).The operation is described as following.

When the I/O buffer transmits a logic low (0V), the gate voltages of MON3 is controlled at VDD, and the node “pd” is biased at 0V to turn on MGP2 .So the node “pr” is coupled to VDD and then the voltage level of node “biasp” is coupled to (VDD-Vt) through MGN2 to turn on MON1. Therefore the logic low can be transmitted from ground through nodes n2 and n1 to the I/O port “PAD”. The dynamic bias circuit detects the voltage level 0V of “PAD”, and feedbacks a bias level as VDD to signal “bias” and pulls the voltage level of node “biasp” from (VDD-Vt) to full VDD. The MGN1 is turned on for its gate voltage level is coupled to VDD. The voltage level of node “pgate” is controlled at VDDIO to turn off MOP1. Then the voltage level of node “pgate1” is coupled to VDD through MGN3 to limit the stress between “pgate1” and “PAD” as VDD. The PMOS MGP1 is turned off for its Vsg=0V. Therefore the logic low can be transmitted to “PAD”

without static current and gate overstress.

When the I/O buffer transmits a logic high (VDDIO), the voltage level of node

“pgate” is controlled at VDD to turn on MOP1. Then “bias” is coupled to VDDIO through

MOP1 to turn on MGN1. And the voltage level of node “pgate1” is coupled to VDD through MGN1 to turn on MOP2. Therefore the logic high (VDDIO) can be transmitted from I/O power supply VDDIO through MOP1 and MOP2 to the I/O port “PAD”. The dynamic bias circuit detects the voltage level “VDDIO” of “PAD”, and feedbacks a bias level as VDDIO to signal “biasp” to turn off MGP1 and MGN3 and turn on MON1. The voltage level of node “n1” is coupled to (VDDIO-Vt) through MON1 and leveled down to (VDD-Vt) through MON2 at node “n2”. The gate voltage of MON3 is controlled at 0V, and the node “pd” is biased at VDD to turn off MGP2. The NMOS MGN2 blocks voltage level “VDDIO” of node “biasp” to protect MGP2. Meanwhile the voltage level of node

“pr” is coupled to near VDD. Therefore the logic high can be transmitted to “PAD” without static current and gate overstress.

When the I/O buffer receives a logic low (0V), the voltage levels of node “ngate” and

“pgate” are controlled at 0V and VDDIO respectively to turn off MON3 and MOP1. And the node “pd” is controlled at VDD to turn off MGP2. The dynamic bias circuit detects the voltage level 0V of “PAD”, and generates a bias level as VDD to signals “biasp” and

“bias”. Therefore the node “pgate1” is coupled to VDD through MGN3 to limit the Vgd of MOP2 at VDD. The NMOS MON1 is turned on because its gate voltage level is charged to VDD. The node “n1” is coupled to 0V through MON1 and the node “n2” is coupled to 0V through MON2. Therefore, there are no leakage current paths and no gate-oxide overstress condition in all devices of the circuit.

When the I/O buffer receives a logic high (VDDHVP), the voltage levels of node

circuit detects the voltage level VDDHVP of “PAD”, and feedbacks a bias level as VDDIO to signals “biasp” and “bias”. Therefore the node “pgate1” is coupled to VDDHVP through MGP1 to turn off MOP2. MGN1 and MGN3 are turned off for their Vgs=0V. The node

“n1” is coupled to (VDDIO-Vt) through MON1 and leveled down to (VDD-Vt) at node

“n2” through MON2 to protect MON3. MGN2 blocks VDDIO of node “biasp” to protect MGP2. The P-well of MON1 is connected to node “n1” to prevent junction breakdown when “PAD” =VDDHVP.

When the I/O buffer receives a logic high (VDDIO), the voltage levels of node

“ngate” and “pgate” are controlled at 0V and VDDIO respectively to turn off MON3 and MOP1. And the node “pd” is controlled at VDD to turn off MGP2. The dynamic bias circuit detects the voltage level VDDIO of “PAD”, and feedbacks a bias level as VDDIO to signals “biasp” and “bias”. Therefore the node “pgate1” is coupled to (VDDIO-Vt) through MGN1 and MGN3. MGP1 is turned off for its Vsg=0V. The node “n1” is coupled to (VDDIO-Vt) through MON1 and leveled down to (VDD-Vt) at node “n2” through MON2 to protect MON3. MGN2 blocks VDDIO of node “biasp” to protect MGP2. Therefore, there are no leakage current paths and no gate-oxide overstress condition in all devices at high voltage input mode.

Fig. 4. 4 The proposed gate tracking circuit of dual supply SGO HVT I/O driver

The voltage table of gate tracking circuit at all operation modes is shown in Table4. 3.

Mode Output

pagate VDDIO VDD VDDIO VDDIO VDDHVP

bias VDD VDDIO VDD VDDIO VDDIO

pagate1 VDD VDD VDD VDDIO-Vt VDDHVP

biasp VDD VDDIO VDD VDDIO VDDIO

biasl VDD ~VDDIO VDD ~VDDIO VDDHVP

PAD 0V VDDIO 0V VDDIO VDDHVP

n1 0V VDDIO-Vt 0V VDDIO-Vt VDDIO-Vt

n2 0V VDD-Vt 0V VDD-Vt VDD-Vt

ngate VDD 0V VDD 0V 0V