Green Bus Coding Stage for Crosstalk Avoidance…

2

1 2 3 4 1 2 2 3 3 4

12 23 34

3( ) ( )

4 ( )

L DD

P f C V

r r r r r r r r r r

d d d

α

α λ

λ

= × × ×

= + + + + ⊕ + ⊕ + ⊕

+ + +

3.3.3 Green Bus Coding Stage for Crosstalk Avoidance

The purpose of green bus coding is to minimize the value of α in Eq. (19) by encoding the signals when λ>2, the design flow of green bus coding as shown in Figure 3.10.

Figure 3.10: Design flow of green bus coding

Therefore, we establish a 32x32 transition state table by calculating α, Table 4 shows the total α value of each patterns transit to other 31 patterns. So we can select 16 transition patterns with minimal values of α as the codeword by avoiding crosstalk.

The 16 patterns is composed of 2 with α_total =400, 8 with α_total =528 (blue mark as shown in Table 4), and 6 with α_total =656 (select from 12 patterns, red mark as shown in Table 4).

Table 4. Total α value of each patterns transit to other 31 patterns

The correspondences between 4-bit data-word and 5-bit codeword are shown in Figure 3.11(a). According to the correspondences, the data-word can be grouped into two set, original set and converted set. When the transmitted data is in the converted set, the green bus coding will convert the data to the original set by one-to-one mapping as Figure 3.11(b). Meanwhile, the converted bit, c4, will be asserted, and c0 and c2 will be inverted and mapped to the original set. X1 and X2 will not be modified all the time. The circuit implementation of green bus coding is also shown in Figure 3.12, including encoder and decoder.

Data words Codewords

Figure 3.11: (a) 4-to-5 Green bus coding scheme (b) Original set and converted set of Green bus code

Figure 3.12: Circuit implementation of green bus coding (a) Encoder (b) Decoder

The circuitry of green bus coding is more simple and effective than other approaches by the joint triplication bus model. Between two adjacent 5-bit codeword, it’s unnecessary to add an extra shielding line to reduce the coupling effect. This is because the boundary data of the 5-bit codeword are set as 0 almost. Certainly, it can achieve more energy saving by inserting a grounded shielding line. It’s a trade-off between wiring area and energy consumption.

The proposed green bus coding has following properties:

(1) Using C4 as detection bit to decide Y0 and Y2. It can simplify the circuitries of encoder and decoder, especially for the decoder.

(2) The encode bit is always equal to the data bit at certain bit positions, which Y1 = Y1 and Y3 = Y3.

(3) Focus on the joint bus and error correction coding scheme, the self-corrected green coding scheme can avoid forbidden overlap condition (FOC) and forbidden pattern condition (FPC) and reduce forbidden transition condition (FTC) to achieve more power saving.

(4) It’s unnecessary to add extra shielding lines to reduce the coupling effect between two adjacent codeword with increasing coding bits.

Chapter4

A Self-Calibrated Voltage Scaling Technique for Reliable Interconnections in Network-on-Chip

4.1 Preliminary

Network-on-chip (NoC) design has been considered an effective solution to integrate multi-core systems and a process independent interconnection architecture . As to the shrinking of processing technologies, the ratio between the interconnection delay and the gate delay will increase in advanced technologies. It indicates on-chip interconnection architectures, such as NoC, will dominate the performance in future system-on-chip (SoC) designs. In addition to today’s multi-core SoC design, power consumption is the major challenge with advanced technologies. Some physical effects in nano-scale technology, unfortunately, will degrade the performance of NoC.

First, coupling capacitances increase significantly in nano-scale technology. Second, decreasing of the operation voltage will make the interconnection more susceptible to noise. Due to crosstalk noises, it not only aggravates the power-delay metrics but also deteriorates the signal integrity.

For on-chip interconnection, three critical issues such as delay, power and reliability have to address. For the delay issue, the propagation delay will be deteriorated by the coupling capacitances. Especially for long global lines, it takes long time to charge/discharge large capacitances. For the power issue, the power dissipation will increase due to both parasitic and coupling capacitances. Finally, the reliability issue of on-chip interconnection will degrade due to noises. In advanced

technologies, circuits and interconnects become even more degraded to noises as well as lower operation voltages. Furthermore, the increasing coupling noises, soft-error rate, bouncing noises decrease the reliability also. In view of these, self-calibration circuitry will become essential in today’s SoC design. Therefore, a joint error correction coding and bus coding scheme is an effective solution to deal with the three challenges. We proposed a novel joint bus and error correction coding scheme, which is called self-corrected green coding scheme as discussed in Chapter 3. It provides NoC platforms energy-efficient and reliable interconnections.

In this Chapter, a novel self-calibrated voltage scaling technique is proposed for the link wires in NoC according to the self-corrected green coding scheme. The self-calibrated voltage scaling technique adjusts the operation voltages by two detection stages, which are crosstalk-aware test error detection stage and run-time error detection stage. The crosstalk-aware test error detection stage detects the error by maximal aggressor fault (MAF) test patterns in the testing mode. The run-time error detection stage detects errors by double sampling data checking technique;

moreover, it provides the tolerance to timing variations. According to the error detections, the self-calibrated voltage scaling technique can reduce the voltage swing for energy reduction and guarantee the reliability at the same time.