Due to the variables in Verilog only have finite precision, the word length of variables in the Matlab platform must be decided by the procedure of Fixed-point.
Figure 5-1 shows the flowchart of Matlab to Verilog design. Fixed-point simulations are performed to decide the word length of variables in the Matlab platform and ensure that these changes will not degrade system performance seriously. This is a trade-off between the cost and the performance. Once the fixed-point simulations are done, the input and output data generated by the Matlab platform will be fed into the Verilog module to verified the correctness of the desired functionality in Verilog. If the output data of Matlab is completely the same as the one of Verilog, the transformation from Matlab to Verilog is done. The data flow of phase recovery is shown in figure 5-2. The whole algorithm of phase recovery can be divided into tow main function blocks, Phase Error Estimation, and Phase Error Compensation. After passing the FFT, the received data will be transformed from time domain to frequency domain. The phase error estimation will take both the outputs of FFT and channel estimation as the inputs. After the phase error is acquired, the phase error compensation will use it to compensate the received data and pass the compensated data to the STBC decoder.
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Figure 5-1 Flowchart of Matlab to Verilog design
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Figure 5-2 data flow chart of phase recovery
Figure 5-3 shows the input/output port definition of phase error estimation. Phase error estimation will take the received pilots and channel frequency responses as the inputs and its outputs will be the estimated phase error. Figure 5-4 is the hardware architecture of phase error estimation. In this block, the four ideal pilots of each antenna will multiply with their own channel frequency responses and be summed up to acquire the ideal received data at the pilot tone. After the ideal received data is carried out, the actual received data will be divided by the ideal received data to acquire the estimated phase error. The gate count of phase error estimation is about 40K in TSMC 0.13µm CMOS process.
Pilot_I Pilot_Q
CLK RESET
H11_I H11_Q
H12_I H12_Q
H13_I H13_Q
H14_I H14_Q
CFO_I
CFO_Q
Figure 5-3 Input/output port definition of Phase Error Estimation
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Figure 5-4 Hardware Architecture of Phase Error Estimation
Figure 5-5 shows the input/output port definition of phase error compensation. Phase error compensation will take the received pilots and the estimated phase error as the inputs and its outputs will be the compensated data.
Figure 5-6 is the hardware architecture of phase error compensation. In this block, it will first sum up the four phase errors estimated by the phase error estimation. Then the summation of the phase errors will be divided by 4 to get the average. The function of abs is to get the amplitude of the average phase error. It will get the summation of the squares of the image part and real part of the average phase error, and then calculate the square root of the summation. The average phase error will be divided by the square root to get the normalized phase error. Once the normalized phase error is carried out, the ACC will sum up the normalized phase error with the previous one and the received data will be compensated by multiplying the conjugate of the normalized phase error. The gate count of phase error compensation is about 200K in TSMC 0.13µm CMOS process.
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PHASE ERROR COMPENSATION
CFO_I*4 CFO_Q*4
DATA_I*56 DATA_Q*56
CLK RESET
Comp_DATA_I*56 Comp_DATA_Q*56
Enable
Out_Valid
Figure 5-5 Input/output port definition of Phase Error Compensation
Figure 5-6 Hardware Architecture of Phase Error Compensation
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Chapter 6
CONCLUSION
Carrier Synchronization plays an important role in MIMO-OFDM systems. The presence of I/Q imbalance in an RF front-end introduces an image interference and the CFO estimation errors degrades the system performance. In this thesis, a pilot-based scheme for the time-varying I/Q imbalance and phase recovery has been proposed. The improvement of adaptive I/Q estimation is about 5 dB under the time-varying I/Q imbalance with variation 30% and the phase recovery can correct the CFO estimation errors effectively. Table 6-1 shows the comparison result of I/Q imbalance with other methods. From this table, the proposed algorithms have lower computational complexity and can satisfy the required system performance. Finally, the phase recovery is implemented by TSMC 0.13 µm CMOS process and the gate count is about 240 K.
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Table 6-1Comparison with other methods
Ref [11] Ref [14] Ref [15] This Work
System SISO 2x2 MIMO 2x1 MIMO 2x2 MIMO
Method FIR Filter &
LS RLS & MMSE LS Adaptive &
LMS
Computational Complexity High High High Low
Packet Format User Defined User Defined IEEE 802.11n IEEE 802.11n
Time-varying Imbalance No No No No
Channel No No No Yes
Bibliography
[1] TGn Sync Group, IEEE P802.11 Wireless LAN - TGn Sync Proposal Technical Specification, Proposal of IEEE802.11n, IEEE Document 802.11-04/889r4,
[2] Wei-Chi Lai and Terng-Yin Hsu, The Study of All-Digital compensation for I/Q Mismatch with Frequency Dependent Imbalance in MMO-OFDM Baseband Designs, 2006.
[3] Jui-Yuan Yu, Ming-Fu Sun, Terng-Yin Hsu, and Chen-Yi Lee, A Novel Technique for I/Q Imbalance and CFO Compensation in OFDM Systems, 23-26 May 2005 Page(s):603-6033 Vol.6 Digital Object Identifier 10.1109/ISCAS.2005.1466014 [4] Hung-Kuo Wei and Chen-Yi Lee, A Frequency Estimation and Compensation
Method for High Sped OFDM-based WLAN System, 2002
[5] Alireza Tarighat, Rahim Bagheri, and Ali H. Sayed, Compensation Schemes and Performance Analysis of IQ Imbalances in OFDM Recievers, IEEE TRANSACTION ON SIGNAL PROCESSING, VOL 53, NO. 8, AUGUST 2005 [6] M. Valkama , M. Renfors, and V. Koivunen, “Compensation of
frequency-selective IQ imbalances in wideband receivers models and algorithms”, Wireless Communications, 2001. (SPAWC '01). 2001 IEEE Third Workshop on Signal Processing Advances in 20-23 March 2001 Page(s):42 – 45
[7] Francois Horlin, Stefaan De Rore, Eduardo Lpoez-Estraviz, Impack of Frequency Offset and IQ Imbalance on MC-CDMA Reception Based on Channel tracking, IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATONS, VOL. 24, NO. 6, JUNE 2006.
[8] Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, IEEE Std 802.11a, 1999
40
[9] M. Valkama , M. Renfors, and V. Koivunen,,.”Blind source separation based I/Q imbalance compensation,” in Proc. IEEE Symposium 2000 on Adaptive Systems for Signal Processing, Communications and Control, Lake Louise, Alberta, Canada, Oct. 2000, pp 310-314.
[10] K.P. Pun, J.E. Franca, C. Azeredo-Leme, C.F. Chan,C.S. Choy, “Correction of frequency-dependent I/Q mismatches in quadrature receivers,” IEEE Electronics Letters, Volume 37, Issue 23, Page(s):1415–1417, Nov 2001.
[11] X. Guanbin, S. Manyuan, L. Hui, “Frequency offset and I/Q imbalance compensation for direct-conversion receivers,” IEEE Transactions Wireless Communications, Volume 4, Issue 2, Page(s):673–680, March 2005.
[12] T.M. Ylamurto, “Frequency domain IQ imbalance correction scheme for orthogonal frequency division multiplexing (OFDM) systems,” IEEE Wireless Communications and Networking, Volume 1, Page(s):20–25, March 2003.
[13] R.M. Rao, B. Daneshrad, “I/Q mismatch cancellation for MIMO-OFDM systems,” 15th IEEE International Symposium Personal, Indoor and Mobile Radio Communications (PIMRC), Volume 4, Page(s):2710-2714, Sept. 2004.
[14] R.M. Rao, B. Daneshrad, “Analog impairments in MIMO-OFDM systems,”IEEE Transactions on Wireless Communications VOL. 5, NO. 12, December 2006.
[15] Alireza Tarighat, Ali H. Sayed, “MIMO OFDM Receivers for Systems with IQ Imbalances, ”IEEE Transactions on Signal Processing, VOL. 53, NO. 9, September 2006