Chapter 4. A novel array-based test methodology for local process
4.2 Design Methodology
4.2.2 Hardware IR Compensation
A hardware IR-compensation technique is used in the proposed array-based test structure to reduce measurement error caused by the large parasitic resistance of the added transmission gates and routing paths. The key concept of this hardware IR compensation is to separate the forcing and sensing paths originally connected at the probe card (as shown Fig. 5.1), and re-connect them at a position very close
Figure 4.8: Layout of the proposed test structure using circuit-under-pad design (CUP) for scribe-line compatible footprints. (a) cross-section view of CUP design, (b) top view of the proposed test structure, and (c) schematic inside each test unit.
to the DUT. Such a connection can reduce the parasitic resistances between a com-pensation point and its corresponding DUT. In our test structure, the approximate distance between the compensation point and DUT is less than 2um. Thus, the parasitic resistance between compensation point and DUT is significantly lowered.
For example, using typical metal resistance values, the parasitic resistance for each connection can easily be reduced to ~ 0.2 Ohm which is substantially lower than the 1 to 30 Ohm for a conventional PCM test-line as described in Fig. 2. Fig. 4.9 shows the whole configuration of the proposed setup, which contains the enhanced Kelvin connection, Agilent 407X SMUs, and a redesigned compensation point. All the DUT’s terminals including drain, source, gate and bulk are compensated by this enhanced Kelvin connection to ensure measurement accuracy. The measurement
error for the configuration of Fig. 4.9 can be calculated by the following equations.
We note that because Ri is much larger than Rsand Rf, to simplify the calculation, the negligible current flowing through Ri is taken to be zero.
Vsense = Vset (4.1)
As Equation 4.2 shows, the compensation error increases as Idut increases.
In order to address this compensation error when Idut is high, we can either reduce the parasitic resistances Rs and Rf by layout engineering, or increase the internal resistance Ri at the SMU. To reduce Rs and Rf, we can increase the size of a transmission gate such that its channel resistance is reduced, or increase the metal routing width. However, a larger transmission gate results in larger leakage [82], and wider metal routing requires more layout space. Therefore, in our hardware compensation, we choose to increase the SMU’s internal resistance Ri to limit the measurement error.
Increasing Ri lowers the difference between Vdut and Vset. Typically, the SMU’s internal resistance in an Agilent 407X tester is a few k Ohm. For in-stance, with Vdut of 1V, the error percentage with a 10k-Ohm Ri and a 300-Ohm Rs is approximately 870Ohm*(Idut/1V) %. This error percentage can be reduced to 45Ohm*(Idut/1V) % if Ri is increased to 200k Ohm. Since the maximum Idut
for most typical device measurements is approximately 2mA, the worst case error percentage can be improved from 1.57% to less than 0.09%, if Ri is increased from 10k Ohm to approximately 200k Ohm. The error percentage slightly increases with Idut for wide device width (>2um). However, a 2mA maximum current level is ad-equate for most applications such as SPICE modeling, process diagnostics, stress, DFM and variation characterization. For a worst case of DUT measurement with Idut=10mA, Ri=200K Ohm and Rs=Rf=300 Ohm, the error will be smaller than 0.44%, which is superior to either a conventional PCM or adaptive voltage com-pensation. However, increasing Ri results in larger voltage convergence time. This technique should, therefore, be used with caution.
Figure 4.9: Schematic of the proposed hardware IR-compensation mechanism.
4.2.3 Voltage Bias Elevation for Measuring Ion
In the previous subsection, we introduced the use of the proposed hardware IR compensation to achieve high measurement accuracy, especially when Idutis high.
However, as shown in Fig. 4.10, the proposed IR compensation technique may create a negative node Vsx beside the transmission gate on the force path of the DUT’s source side. During the IR compensation, the value of Vsx depends on Idut and the parasitic resistance of metal routing and transmission gates, Rs. Vsx is in the range
of ~-0.2 to ~-1.0V in the example of Fig. 4.10. Thus, if Idut or Rs become too large, Vsx at the transmission gate’s input node will become a large negative voltage, which may turn on the diode from source to substrate on the transmission gate and result in malfunction if Vsx is below -0.6V.
Figure 4.10: An example of the negative node created without applying the proposed voltage bias elevation technique.
Considering the case of Ion measurement for a core logic transistor with Vdd=1.0V for example, before the OP Amp settles, the voltage at the drain com-pensation point would initially be below 1.0V due to the IR drop. Vf orce would continue increasing until the voltage of the compensation point Vdut reaches 1.0V.
Vf orce would be elevated to approximately 1.0V+Idut*Rf. This does not present a problem on the forcing path of the DUT’s drain side as long as Vdxis still below Vdd
(i.e., 2.5V). However, it would cause a negative node on the force path of the DUT’s source side. The source-voltage setting of the DUT is 0V for Ion measurement.
The voltage at the input of the transmission gate would thus be decreased below the diode’s turn-on voltage (about -0.6V) due to the parasitic resistance of metal
routing and transmission gates, especially when Idut is high. This would turn on the transmission gate’s drain to bulk diode. As shown in the following equation, Vsx, and a corresponding ”elevation” voltage Velv, can be roughly calculated given Idut, the diode’s turn-on voltage Vdt, and the transmission gate resistance RT G.
Vsx = Idut· 2 · RT G >−Vdt
Velv = −Vsx (4.3)
If Vsx <−Vdt, the current measured by the SMU would be the diode’s forward biased current, not the DUT current. To prevent this , the voltage bias of all the DUT’s terminals are elevated to a positive voltage Velv during Ion measurement to eliminate the negative voltage at the source path. This bias voltage Velv is applied to Vset (thus also increasing Vdx), Vg, Vd, Vs, and Vb. The elevated voltage does not affect the electrical behavior of the measured DUT because the same voltage elevation is applied to all terminals concurrently. In addition, the power supply of the periphery circuitry can be overdriven to 3.3V to enlarge the compensation margin, i.e 3.3/2.5V VDD for a 2.5/1.8V I/O process. Figs. 4.10 and 4.11 respectively, show an example without and with application of voltage bias elevation.
4.2.4 Leakage-Current Cancellation for Measuring Iof f
Another important MOSFET parameter to be measured is the off-state leak-age current Iof f. When measuring current, a SMU senses not only the DUT current, Idut, but also the leakage current from periphery circuitry. For Ion measurement, the leakage current from peripheral circuitry does not affect the measurement ac-curacy since this leakage current is much smaller than Ion. However, this leakage
Figure 4.11: No forward biased current on the transmission gate is generated after ap-plying voltage bias elevation (Velv=0.5V).
current can significantly affect the accuracy of Iof f measurement. The sources of this leakage current include (1) the leakage from peripheral circuitry transistors and (2) the leakage from the transmission gates on selection paths. The second of these typically dominates the total leakage current. The leakage current from the trans-mission gates may result from the N+/PW and P+/NW junction leakage, and gate to drain leakage on both the pMOS and nMOS of the transmission gates. There are 64+4 leakage current paths created by the transmission gates in the proposed test structure as shown in Fig. 4.12 (64 gates for each column and 4 gates for each row).
In order to reduce the current from these leakage paths, we use I/O devices (having relatively thicker gate oxide and longer channel length) for designing the periphery circuitry. Also, we propose a leakage-current-cancellation technique for our array-based test structure. This leakage-current cancellation elevates all the DUT’s terminals to an optimal voltage, similar to the voltage elevation technique described in the previous subsection. The operating principle of this leakage-current cancellation is to set the voltage of the DUT’s drain node such that leakages from the
Figure 4.12: Possible leakage paths in the proposed array-based test structure. The thick line indicates the selected path. The background leakage current includes the leakage from both the selected and unselected paths.
nMOS and pMOS of each transmission gate on the 68 leakage paths can be balanced.
Figs. 4.13 and Fig. 4.14 respectively illustrate the leakage current before and after employing the voltage elevation technique. Before voltage elevation, the voltage difference from the DUT’s drain to both the nMOS gate and the pMOS substrate is 1.5V, but the voltage difference from the DUT’s drain to both the nMOS substrate and the pMOS gate is only 1.0V. This unbalanced voltage difference may result in a large current on this transmission gate as shown in Fig. 4.13. After the voltage of the DUT’s drain is elevated to an optimal value, the voltage differences from the DUT’s drain to each nMOS or pMOS gate, or to the substrate, are all equal, such that the leakage currents from this transmission gate cancel out one another
as illustrated in Fig. 4.14.
Figure 4.13: Larger background leakage due to unbalanced leakage paths before applying voltage bias elevation.
Figure 4.14: Reducing the leakage current by balancing the leakage paths with optimized voltage bias elevation.
If all transmission gates were perfectly fabricated, all nMOS and pMOS should be completely symmetric. In this ideal case, the optimized voltage at the DUT’s drain should be half of the transmission gate VDD, i.e., 1.25V in our exam-ple. However, in reality the fabrication of each transmission gate is also affected by process variation. Thus, when measuring Iof f, the values of both VDD and the elevated voltage at the DUT’s terminals may be swept to find an optimal voltage
to minimize the leakage current from the 68 leakage paths during the measurement.
The background leakage can be optimized by offsetting the drain voltage slightly from half VDD. Fig. 4.15 plots Iof f as a function of the drain voltage offset from half VDD for the 64 DUTs in the array for one wafer (9 die tested on each wafer, with 1 array in each die). Typically, the minimum DUT off current can be obtained at a drain voltage fairly close to half VDD. In this example, the sweep confirmed that the optimal voltage was quite close to half VDD, as Iof f is observed to significantly increase with a non-zero offset voltage. However, the optimal drain voltage might not be exactly half VDD for all processes. It might be slightly above or below half VDD for different processes depending on the difference between the NMOS and PMOS gate and junction leakage in the transmission gates, and sweeping the offset voltage as done in Fig. 4.15 permits confirmation or correction of the optimal offset voltage. Of course depending on the range and resolution of the offset voltage sweep, additional test time will be required to obtain this data. In this example, based on the data of Fig. 4.15, a voltage of half VDD was determined to be adequate. We further emphasize that because long-channel thick-oxide IO transistors are used in the transmission gates, the offset voltage is relatively insensitive to process varia-tion. In practical applications, a quick confirmation of the optimal offset voltage can be obtained with two additional Iof f measurements, i.e. for positive and negative values of a single offset voltage. Further adjustment of the offset voltage need only be performed if it is shown to be necessary by these two measurements, in which case the offset voltage can be adjusted iteratively to minimize Iof f to the desired precision, at the cost of 2 additional Iof f measurements for each successive iteration.
Because the need for offset voltage adjustment results from leakage imbalance in the periphery circuits, and these are long wide IO devices relatively less susceptible to local process variation, if such adjustment is necessary, it is likely to only be needed
once for each DUT array. Local process variation causes variation in Iof f for dif-ferent DUTs in the same array, but it is unlikely to affect the offset voltage which must be applied to the periphery to minimize the measured Iof f value.
Figure 4.15: Background leakage reduction by offset voltage from half VDD for the 64 DUTs in the array for 1 wafer (9 die/wafer with 1 array/die).