Array-based test structure result

The test speed improvement of OP-based Vt measurement is most significant in array-based test structures. In addition to the test time savings from reducing

~10 force-measure iterations to 1, the array-based test structure avoids the time required for the connect and disconnect operations between SMUs and testline IO pads for measurement of successive DUTs which must be performed before the force-measure iterations can begin. Typically, the time required for connect and disconnect operations, which are performed by mechanical switches, is about 1 ms.

However, the time required for changing and latching addresses for DUT selection in array-based test structures is less than 1 us which is much faster than the connect and disconnect mechanical operations. In practice, for array-based test structure measurement, connection between SMU and pad is performed at the first address and disconnection is performed at the last address because the same SMUs are

used for the force and sense terminals of all DUTs. Moreover, the testing time overhead can be further improved in array-based test structure by elimination of prober index time. In general, the prober index time is typically a few hundred ms if the required prober chuck displacement is less than 1 mm. In this experiment, a test time comparison was performed between (A) non-array-based test structures, and (B) array-based test structure. Both cases include ~ 1k DUTs with different W/L combinations. However, in case (A), non-array test structures required more a larger number of testlines and thus more layout area. Typically, only 8 DUTs can be placed in one non-array testline due the constraint that DUTs must not have excessive sharing of I/O pads. As a result, 1k DUTs requires 1000/8=125 testlines in case (A). The Vt of each DUT was measured by the proposed methodology under two different test conditions: 1) non-array DUTs in case A, which require a SMU connect and disconnect for each individual DUT, and 2) an array-based test structure in case (B), which only requires a connect and disconnect for operation for the first and last addresses, respectively. As can be seen in Table II, the time required specifically for the 1k DUT Vt measurements is approximately 6000 ms for both cases (A) and (B). However, case (A) it requires additional overhead of 1000 ms from SMU connect and disconnect operations. Moreover, case A utilizes 125 probe card touch downs instead of the single touch down of case (B). Therefore, case (A) requires 125 prober chuck displacements during measurement. Assuming a prober index time of 200 us, case(A) incurs an additional penalty of approximately 125*200 ms are required for case (A). As a result, the total test time is approximately 32,000 ms and 6,002 ms for the proposed Vt measurement on non-array and array-based test structures, respectively. The test speed is further improved by factor of 5X by taking advantage of a single connect/disconnect and elimination of the prober index time during measurement of the array-based test structure.

non-array DUT array-based DUT

# only measurement ~6000 ms ~6000 ms

# connect and disconnect ~1000ms ~2ms

# prober index time ~1000/8*200ms 0ms

# total testing time ~32000sec ~6002ms

Table 5.2: Test time comparison of OP-based Vt measurement between stand-alone DUT and array-based DUT.

Conclusion

In this thesis, we, first, have presented a novel dummy-fill flow, which applies boolean mask operations to directly generate the mask layers with dummy patterns inserted, and performs dummy generation and mask computation at the foundry simulta-neously with dummy fill and post-dummy simulation at the design house. The proposed flow not only improves the efficiency of dummy generation, but also elim-inates the delays in tape-out due to dummy insertion and post-dummy simulation, and dramatically reduces the tape-out GDS file size, enabling more rapid first sil-icon delivery. In comparison with a conventional dummy-fill flow currently widely used throughout the IC industry, the proposed dummy-fill flow can achieve bet-ter patbet-tern uniformity with less runtime and smaller GDS-file size. The savings in runtime and GDS-file size will be even more significant in future advanced process technologies as more short-range dummy patterns with smaller pattern dimensions are required. Secondly, we have demonstrated a novel design verification flow, which verifies mask generation algorithms by automated direct comparison with the design netlist utilizing currently available physical verification EDA tools. Minimal effort is required to create both the MVS runset and the virtual mask set GDS for ver-ification. The experiments described above demonstrate that MVS automatically detects common errors. As process technologies continue to scale, and the IC in-dustry is challenged by more complex mask generation and requirements for custom

118

devices, the proposed design verification flow will become increasingly critical to insuring first silicon success. Next, we successfully developed an array-based test structure and a corresponding novel test methodology for overcoming the IR-drop from parasitic resistance and the leakage current from the control circuitry, which are challenges inherent to any array-based characterization technique. We introduce the technique of hardware IR compensation to address the parasitic IR drop, and the combination of voltage bias elevation and leakage current cancellation to perform ef-ficient, highly accurate current measurements on a large device array. The proposed array-based test structure can fit into the pad frame of a traditional PCM testline and can be placed on a scribe line for production process monitoring. Measurements with the proposed structure have demonstrated accuracy comparable to the PCM testline, but a much larger data volume can be gathered with the same pad frame area. Also, its DUT array size can be further extended for statistical SPICE mod-eling. A series of experiments were conducted on both mature and newly developed process technologies to validate the effectiveness and the superiority of the overall proposed test structure and methodology. As one example of the application of this technique to perform valuable process characterization, we demonstrate the use of a version of this structure to collect local V_th mismatch data for an array of MOSFET pairs. Finally, we successfully developed a testing methodology by using OP-based SMU to speed up the Vth measurement. By using the proposed techniques, the Vth testing speed can improved by 5~10 times with better accuracy about 0.15mV.

Also, combining with a array-based test structure design, ~ 1k FET the test time of Vt measurements can be further improved by a factor of 5X due to connect, dis-connect and prober index time saving. A series of experiments were conducted on both mature and newly developed process technologies to validate the effectiveness and the superiority of the overall proposed test structure as well its application.

[1] John M. Cohn, David J. Garrod, Rob A. Rutenbar, L. Richard Carley ”Analog Device-Level Layout Automation,” Kluwer Academic Publishers Norwell, MA, USA, 1994.

[2] Florin Balasa, Sarat C. Maruvada, and Karthik Krishnamoorthy ”On the Ex-ploration of the Solution Space in Analog Placement With Symmetry Con-straints,” IEEE Transactions On Computer-Aided Design Of Integrated Cir-cuits And Systems, pp. 177–191, 2004.

[3] Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang ”Novel Full-Chip Gridless Routing Considering Double-Via Insertion,” IEEE Design Automation Con-ference, pp. 755–760, 2006.

[4] Kuang-Yao Lee, Ting-Chi Wang, Kai-Yuan Chao ”Post-Routing Redundant Via Insertion and Line End Extension with Via Density Consideration,” IEEE International Conference on Computer-Aided Design, pp. 633–640, 2006.

[5] Olivier Rizzo and Hanno Melzner ”Concurrent Wire Spreading, Widening, and Filling,” IEEE Design Automation Conference, pp. 350–353, 2007.

[6] Ming-Chao Tsai, Yung-Chia Lin, Ting-Chi Wang ”An MILP-Based Wire Spreading Algorithm for PSM-Aware Layout Modification,” IEEE Asia and South Pacific Design Automation Conference, pp. 364–369, 2008.

120

[7] V. Kheterpal, V. Rovner, T. G. Hersan, D. Motiani, Y. Takegawa, A. J. Stro-jwas, and L. Pileggi ”Design methodology for IC manufacturability based on regular logic-bricks” Annual ACM IEEE Design Automation Conference, pp.

353–358, 2005.

[8] Atsush Kurokawa, Toshiki Kanamoto, Akira Kasebe, Yasuaki In0ue, and Hi-roo Masuda ”Efficient capacitance extraction method for interconnects with dummy fills,” IEEE Custom Integrated Circuit Conference, pp. 485–488, 2004.

[9] Andrew B. Kahng, Kambiz Samadi ”CMP Fill Synthesis: A Survey of Recent Studies,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 3–19, 2008.

[10] Chih-Ju Hung ”Diamond metal-filled patterns achieving low parasitic coupling capacitance,” U.S. Patent 6,998,716

[11] Mark M. Nelson ”Optimized pattern fill process for improved CMP unifor-mity and interconnect capacitance,” University/Government/Industry Micro-electronics Symposium, pp. 374–375, 2003.

[12] Ruiqi Tian, D.F. Wong, Robert Boone ”Model-based dummy feature place-ment for oxide chemical-mechanical polishing manufacturability,” IEEE Design Automation Conference, pp. 667–670, 2000.

[13] Yu Chen, Andrew B. Kahng, G. Robins, Alexander Zelikovsky ”Practical iter-ated fill synthesis for CMP uniformity,” IEEE Design Automation Conference, pp. 671–674, 2000.

[14] Maharaj Mukherjee, Kanad Chakraborty ”A Randomized Greedy Algorithm for the Pattern Fill Problem for DFM Applications,” International Symposium on Quality Electronic Design, pp. 344–347, 2008.

[15] Charles Chiang, Jamil Kawa ”Design for Manufacturability and Yield for Nano-Scale CMOS,” Springer, 2007.

[16] Jianfeng Luo, Qing Su, Charles Chiang, Jamil Kawa ”A Layout dependent full-chip copper electroplating topography model,” IEEE International Conference on Computer-Aided Design, pp. 133–140, 2005.

[17] Subarna Sinha, Jianfeng Luo, Charles Chiang ”Model based layout pattern dependent metal filling algorithm for improved chip surface Uniformity in the copper process,” IEEE Asia and South Pacific Design Automation Conference, pp. 1–6, 2007.

[18] R. Li, L. Yu, H. Xin, Y. Dong, K. Tao, and C. Wang ”A comprehensive study of reducing the STI mechanical stress effect on channel-width-dependent Idsat”

Semiconductor Science and Technology , Vol.22, pp. 1292–1297, 2007.

[19] Oliver Pohland, Julie Spieker, Chih-Ta Huang, Srikanth Govindaswamy, and Artur Balasinski ”New type of dummy layout pattern to control ILD etch rate”

Proceedings of the SPIE, , Vol. 6798, pp.679804, 2007.

[20] Nakao, Shuji; Tsujita, Kouichirou; Arimoto, Ichiriou; Wakamiya, Wataru

”0.32-um pitch random line pattern formation by dense dummy pattern and double exposure in KrF wavelength” Proceedings of the SPIE, , Vol. 4000, pp.

1123–1133, 2000.

[21] Brent A. Anderson, Howard S. Landis, and Edward J. Nowak, ”Variable overlap of dummy shapes for improved rapid thermal anneal uniformity” US patent 7,537,941 B2

[22] Laurent Remy, Philippe Coll, Fabrice Picot ”Metal Filling Impact on Standard Cells : Definition of the Metal Fill Corner Concept,” Proceedings of the 21st

annual symposium on Integrated circuits and system design, September 1–4, 2008.

[23] Oliver Pohland, Julie Specker, Chih-Ta Huang, Srikanth Govindaswamy, and Arthur Balasinski ”New Type of Dummy Layout Pattern to Control ILD etch Rate,” Proc. SPIE Vol. 6798, 679804, 2007.

[24] Y. Uematsu, ”Integrated circuit device having dummy pattern effective against micro loading effect” US Patent 5,598,010

[25] James A. Wilmore ”Efficient boolean operations on IC masks,” IEEE Design Automation Conference, pp. 571–579, 1981.

[26] Ulrich Lauther ”An O(N log N) algorithm for boolean mask operations,” IEEE Design Automation Conference, pp. 555–562, 1981.

[27] Young-Mi Kim, Sang-Uk Lee, Jea-Hyun Kang, Jea-Hee Kim, and Kee-Ho Kim

”Application of modified jog-fill DRC rule on LFD OPC flow” Photomask technology. Conference, Vol. 6730(3), pp.67303W.1–67303W, 2007.

[28] Todd J. Wagner, ”A HIERARCHICAL APPROACH FOR LAYOUT VERSUS CIRCUIT CONSISTENCY CHECK” 17th conference on Design , pp.270-276, 1980

[29] Todd J. Wagner, ”HIERARCHICAL LAYOUT VERIFICATION” Design Automation Conference, pp.848-849, 1984

[30] Mohy, Ahmed ; Makarem, Mohamed Abul, ”A robust and automated method-ology for LVS quality assurance” Design and Test Workshop (IDT), 2009 4th International

[31] Watts, J. Ke-Wei Su Basel, M. ”Netlisting and Modeling Well-Proximity Ef-fects” Electron Devices, IEEE Transactions on devices, 2006 Volume: 53, Issue:

9 2179-2186

[32] Graphics, M. (n.d.). ”Reduce Cycle Time with Revolutionary New Capabilities from Calibre nmDRC” Mentor, October 20, 2009

[33] Michael Orshansky, Sani R. Nassif, and Duane Boning, Design for Manufac-turability and Statistical Design, A Constructive Approach, ISBN 978-0-387-30928-6

[34] James A. Wilmore ”Efficient boolean operations on IC masks,” IEEE Design Automation Conference, pp.571-579, 1981.

[35] Wlrich Lauther ”An O(N log N) algorithm for boolean mask operations,” IEEE Design Automation Conference, pp.555-562, 1981.

[36] Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang ”Novel Full-Chip Gridless Routing Considering Double-Via Insertion,” IEEE Design Automation Con-ference, pp.755-760, 2006.

[37] Kuang-Yao Lee, Ting-Chi Wang, Kai-Yuan Chao ”Post-Routing Redundant Via Insertion and Line End Extension with Via Density Consideration,” IEEE International Conference on Computer-Aided Design, pp.633-640, 2006.

[38] Olivier Rizzo and Hanno Melzner ”Concurrent Wire Spreading, Widening, and Filling,” IEEE Design Automation Conference, pp.350-353, 2007.

[39] Ming-Chao Tsai, Yung-Chia Lin, Ting-Chi Wang ”An MILP-Based Wire Spreading Algorithm for PSM-Aware Layout Modification,” IEEE Asia and South Pacific Design Automation Conference, pp.364-369, 2008.

[40] Ghani, T. et al; ”A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors,” IElectron Devices Meeting, 2003., pp.11.6.1-11.6.3, 2003.

[41] Neil Weste, David Harris; ”CMOS VLSI Design: A Circuits and Systems Perspective (3rd Edition),” ISBN: ISBN-13: 978-0321149015,

[42] Diaz, C.H. et al; ”32nm gate-first high-k/metal-gate technology for high perfor-mance low power applications,” Electron Devices Meeting, 2008. IEDM 2008.

IEEE International, pp.11-4, 2008.

[43] X. Chen et al; ”A cost-effective 32nm High-K metal-gate CMOS technology for low-power applications with single-metal/gate-first process,” VLSI Tech.

Symp., pp.88-89, 2008.

[44] Chris Spence et al; ”Mask data volume: historical perspective and future requirements,” 22nd European Mask and Lithography Conference , Proc. SPIE, Vol. 6281.

[45] Graphics, M. (n.d.). ”Appendix C: GDS II Format. Retrieved October 20, 2009” Computer Aids for VLSI Design, 1994

[46] Graphics, M. (n.d.) ”Reduce Cycle Time with

Rev-olutionary New Capabilities from Calibre nmDRC,”

http://www.mentor.com/products/ic_nanometer_d esign/verification-signoff/physical-verification/calibre-nmdrc/, October 20, 2009

[47] ”Technology-Leading Physical Verification Solution for 45nm and Above ”

http://www.synopsys.com/tools/implementation/physicalverification/pages/hercules.aspx, 2009

[48] K. Bernstein, et al., ”High-performance CMOS variability in the 65-nm regime and beyond”, IBM Journal of Research and Development , vol.50, no.4.5, pp.433-449, July 2006.

[49] Michihiro Kanno, et al., ”Empirical Characteristics and Extraction of Over-all Variations for 65-nm MOSFETs and Beyond”, Empirical Characteristics and Extraction of Overall Variations for 65-nm MOSFETs and Beyond,” VLSI Technology, 2007 IEEE Symposium on , vol., no., pp.88-89, 12-14 June 2007.

[50] Michael Orshansky, et al. ”Design for Manufacturability and Statistical Design, A Constructive Approach”, ISBN 978-0-387-30928-6.

[51] B. Stine, et al. ”Analysis and Decomposition of Spatial Variation in Integrated Circuit Processes and Devices”, Semiconductor Manufacturing, IEEE Trans-actions on , vol.10, no.1, pp.24-41, Feb 1997.

[52] M. Orshansky, L, Milor and C. Hu, ”Characterization of Spatial Intrafield Gate CD Variability, Its Impact on Circuit Performance, and Spatial Mask-Level Correction”, Semiconductor Manufacturing, IEEE Transactions on , vol.17, no.1, pp. 2- 11, Feb. 2004.

[53] Masaharu Yamamoto, et al. ”Development of a Large-Scale TEG for Evaluation and Analysis of Yield and Variation”, Semiconductor Manufacturing, IEEE Transactions on , vol.17, no.2, pp. 111- 122, May 2004.,

[54] Nigel Drego, Anantha Chandrakasan, and Duane Boning, ”A Test-Structure to Efficiently Study Threshold-Voltage Variation in Large MOSFET Arrays”, Quality Electronic Design, 2007. ISQED ’07. 8th International Symposium on , vol., no., pp.281-286, 26-28 March 2007.,

[55] Sang-Hoon Lee, *Dong-Yun Lee, Tae-Jin Kwon, Joo-Hee, Young-Kwan Park,

”An Efficient Statistical Model using Electrical Tests for GHz CMOS Devices”, Statistical Metrology, 2000 5th International Workshop on , vol., no., pp.72-75, 2000.

[56] Keiji Nagase, Shin-ichi Ohkawa, Masakazu Aoki, and Hiroo Masuda, ”Variation Status in l00nm CMOS Process and Below”, Microelectronic Test Structures, 2004. Proceedings. ICMTS ’04. The International Conference on , vol., no., pp.

257- 261, 22-25 March 2004.

[57] H. Tsuno, et al. ”Advanced Analysis and Modeling of MOSFET Characteris-tic Fluctuation Caused by Layout Variation”, VLSI Technology, 2007 IEEE Symposium on , vol., no., pp.204-205, 12-14 June 2007.

[58] Kanak Agarwal, et al. ”A Test Structure for Characterizing Local Device Mis-matches”, 2006 SVLSI Circuits, 2006. Digest of Technical Papers. 2006 Sym-posium on , vol., no., pp.67-68, 0-0 0.

[59] Y. Z. Xu, C. S. Chen, J. I. Watt, ”Investigation of 65 nm CMOS transistor local variation using a FET array”, Solid-State Electronics, pp. 1244-1248, 2008, [60] Chris Jakubiec, et al. ”An Integrated Test Chip for the complete

Character-ization and Monitoring of a 0.25um CMOS Technology that fits into scribe line structures 150um by 5,000um” , Microelectronic Test Structures, 2003.

International Conference on , vol., no., pp. 3- 63, 17-20 March 2003.,

[61] Naoki Izumi, Hiroji Ozaki, Yoshikazu Nakagawa, Naoki Kasai, and Tsunetoshi Arikado, ”Evaluation of Transistor Property Variations Within Chips on 300-mm Wafers Using a New MOSFET Array Test Structure”, Semiconductor Manufacturing, IEEE Transactions on , vol.17, no.3, pp. 248- 254, Aug. 2004.,

[62] K. Doong, et al., ”Field-Configurable Test Structure Array (FC-TSA): En-abling Design for Monitor, Model, and Manufacturability”, Semiconductor Manufacturing, IEEE Transactions on , vol.21, no.2, pp.169-179, May 2008.,

[63] R.W. Gregor, et al., ”On the relationship between topography and transistor matching in an analog CMOS technology”, IElectron Devices, IEEE Transac-tions on , vol.39, no.2, pp.275-282, Feb 1992.,

[64] C Abel, C. Michael, M. Ismail, C. S. Teng, R. Lahri, ”Characterization of transistor mismatch for statistical CAD of submicron CMOS analog circuits”, Circuits and Systems, 1993., ISCAS ’93, 1993 IEEE International Symposium on , vol., no., pp.1401-1404, 3-6 May 1993.,

[65] J. Bastos, M. Steyaert, B. Graindourze, W. Sansen, ”Matching of MOS tran-sistors with different layout styles”, ICMTS 1996. Proceedings. 1996 IEEE International Conference on , vol., no., pp.17-18, 25-28 Mar 1996.,

[66] Pelgrom MJM, Duinmaijer ACJ, Welbers APG, ”Matching Properties of MOS Transistors”, Matching properties of MOS transistors,” Solid-State Circuits, IEEE Journal of , vol.24, no.5, pp. 1433- 1439, Oct 1989.

[67] K. Bernstein, D. J. Frank, A. E. Gattiker, W. Haensch, B. L. Ji, S. R. Nassif, E. J. Nowak, D. J. Pearson, N. J. Rohrer, High-performance CMOS variability in the 65-nm regime and beyond, IBM J. RES. DEV. VOL. 50 NO. 4/5 JULY/SEPTEMBER 2006

[68] Michihiro Kanno, Akira Shibuya, Masao Matsumura, Kazuhiro Tamura, Hi-toshi Tsuno,Shigetaka Mori, Yuzo Fukuzaki, Tetsuo Gocho, Hisahiro Ansai and

Naoki Nagashima, Empirical Characteristics and Extraction of Overall Varia-tions for 65-nm MOSFETs and Beyond, 2007 Symposium on VLSI Technology Digest of Technical Papers

[69] Michael Orshansky, Sani R. Nassif, and Duane Boning, Design for Manufac-turability and Statistical Design, A Constructive Approach, ISBN 978-0-387-30928-6

[70] B. Stine, D. Boning and J. Chung, Analysis and Decomposition of Spatial Variation in Integrated Circuit Processes and Devices, IEEE Transactions on Semiconductor Manufacturing, Vol. 10, No 1., 1997.

[71] M. Orshansky, L, Milor and C. Hu, Characterization of Spatial Intrafield Gate CD Variability, Its Impact on Circuit Performance, and Spatial Mask-Level Correction, IEEE Trans. On Semiconductor Manufacturing, Vol. 12, No. 1, 2004.

[72] Masaharu Yamamoto, Development of a Large-Scale TEG for Evaluation and Analysis of Yield and Variation, IEEE TRANSACTIONS ON SEMICONDUC-TOR MANUFACTURING, VOL. 17, NO. 2, MAY 2004

[73] Nigel Drego, Anantha Chandrakasan, and Duane Boning, A Test-Structure to Efficiently Study Threshold-Voltage Variation in Large MOSFET Arrays, Proceedings of the 8th International Symposium on Quality Electronic De-sign(ISQED’07),

[74] Sang-Hoon Lee, *Dong-Yun Lee, Tae-Jin Kwon, Joo-Hee, Young-Kwan Park, An Efficient Statistical Model using Electrical Tests for GHz CMOS Devices, 2000 5th INTERNATIONAL WORKSHOP ON STATISTICAL METROL-OGY 2000;72-75

[75] Keiji Nagase, Shin-ichi Ohkawa, Masakazu Aoki, and Hiroo Masuda, Variation Status in l00nm CMOS Process and Below, Proc. IEEE 2004 Int. Conference on Microelectronic Test Structures, Val 17. March 2004; 257-261

Ghani, T. (Intel) et al., A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors; 2003 IEEE International Electron Devices Meeting, IEDM ’03 Technical Digest. 8-10, Dec.

2003 Page(s):11.6.1 - 11.6.3.

[76] Ghani, T et al., A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors, 2003 IEEE Interna-tional Electron Devices Meeting, IEDM ’03 Technical Digest. 8-10, Dec. 2003 Page(s):11.6.1 - 11.6.3.

[77] Chien-Hao Chen et al., Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device ap-plication, 2004. Digest of Technical Papers.15-17 June 2004 Page(s):56 V57 [78] H. Tsuno, K. Anzai, M. Matsumura, S. Minami, A. Honjo, H. Koike, Y. Hiura,

A. Takeo, W. Fu, Y. Fukuzaki, M. Kanno, H. Ansai and N. Nagashima, Ad-vanced Analysis and Modeling of MOSFET Characteristic Fluctuation Caused by Layout Variation, 2007 Symposium on VLSI Technology Digest of Technical Papers 204-205

[79] Kanak Agarwal, Frank Liu, Chandler McDowell, Sani Nassif, Kevin Nowka, Meghann Palmer, Dhruva Acharyya, Jim Plusquellic, A Test Structure for Characterizing Local Device Mismatches, 2006 Symposium on VLSI Circuits Digest of Technical Papers

[80] Y. Z. Xu, C. S. Chen, J. I. Watt, Investigation of 65 nm CMOS transistor local variation using a FET array, Soild-State Electrinics, 52 (2008) 1244-1248

[80] Y. Z. Xu, C. S. Chen, J. I. Watt, Investigation of 65 nm CMOS transistor local variation using a FET array, Soild-State Electrinics, 52 (2008) 1244-1248