Hysteresis Delay Cell

The HDCs [23-25], or namely Schmitt triggers, were widely used in digital and analog circuits for waveform shaping under noisy environment. As shown in Fig. 3.2, the switching point of CMOS inverter circuits is fixed at the average of high level voltage and low level voltage because the PMOS and NMOS are both in the saturation region. But the output signal of HDC circuits is filtered by the high level and low level threshold voltage, donated as V₊ and V₋, respectively. There exists an extra delay between the output of the inverter and HDC due to the hysteresis phenomenon.

Fig. 3.3 describes the transfer function of HDC. The Boolean logical function of HDC in Fig. 3.3 is the same as an inverter gate. In forward switching path, the voltage of output (VOUT) remains high level until the voltage of input (VIN) increases to V+. Then, the output ties to the low voltage. Oppositely, when VIN decreases to V-, VOUT

switches to the high level voltage. The hysteresis voltage width of HDC is defined as equation (3-2).

− +−

=V V

V_hw (3-2)

The hysteresis width presents the output from the cross-talk noise and supply noise on clock and supply power, and also increases the response time of HDC circuits.

However, the feature of hysteresis, or non-sensitivity with input, can provide a long delay in place of lots of cascading inverters.

There are three common HDC in the following sections, including Rabaey [23], Dokic [24] and Sarawi [25] architecture. We attempt to analyze the power consumption and compare with the standard cells in UMC 90 nm CMOS technology.

Fig. 3.2. Output signals through inverter and HDC.

Fig. 3.3. Transfer function of HDC.

3.1.1 Rabaey Architecture

The HDC with Rabaey architecture was proposed as shown in Fig. 3.4 [23].

There are three inverters in this architecture. The transfer function of Rabaey’s HDC is different from that in Fig. 3.3. The Boolean logic of this Rabaey architecture is the same as a buffer cell.

The static behavior of Rabaey architecture is stated as follows. In the beginning, we assume the input voltage VIN is in high level voltage VDD and the output voltage is tied to low. When VIN decreases to a certain voltage V-, the mp3 and mn4 invert the output voltage to VDD. Therefore, the output feedbacks to mp3 and mn4 to speed up the transition and produce a clean output signal [23]. The low level switching point V

-is determined by the trans-istor mp1, mn1 and mn2. The analys-is as forward switching is similar to the above. However, Rabaey HDC consumes large power dissipation due to the short current path.

(a) (b)

Fig. 3.4. Rabaey HDC (a) Circuits (b) Schematic.

3.1.2 Dokic Architecture

There is Dokic architecture of HDC as shown in Fig. 3.5 [24]. The transfer function is the same in Fig. 3.3 as well. It can be extended to a NOR and NAND type HDC. When the input voltage VIN is equal to VDD, mp1 and mp2 are in cut off region, and mn1 and mn2 are turned on. So, the voltage of output VOUT is equal to ground resulting mn3 in cut off region and mp3 in saturation region. While VIN decreases to V-, mp1 and mp3 act as a saturated enhancement-mode inverter. Transistor mp2 turns on as well, providing a charging path from VDD to output. Oppositely, if VIN increases to V+, mn1, mn2 and mn3 are on. Then, there is a discharging path from output to ground.

These obvious short current paths bring about the major power consumption in the Dokic HDC.

Fig. 3.5. Dokic HDC.

3.1.3 Sarawi Architecture

Fig. 3.6 illustrates Sarawi HDC [25] which is designed by inverter chain internally cascaded with a footer and a header. Fig. 3.3 depicts the transfer function.

The operation of this HDC circuit can be described as follows. First, suppose the initial input voltage VIN is VDD, so that the mn2 is on and the mp2 is in cut off region, which implies mn3 is turned off, mp3 is turned on, mn1 is on and mp1 is off.

Transistor mn2 remains on and mp2 remains off until VIN decreases to a certain voltage V-, at which output, VOUT switches from a low to a high value. The similar behavior as forward switching with mp2, mn2 and mn1 is observed as follows. When a low level voltage is applied to VIN, VOUT goes to VDD. VOUT would switch from VDD

to ground until VIN increases into the high level threshold voltage V+ and triggers the pull-down network. Because of the lack of directly short current path, the longer delay and less power consumption can be expected in Sarawi HDC.

Fig. 3.6. Sarawi HDC.

3.1.4 Comparison

Table 3.2 lists the performance comparisons with the above HDCs and the standard cells in UMC SPHVT 90 nm CMOS technology, including BUFM2H, BUFM4H, BUFM8H, DEL1M1H, DEL1M4H and DEL2M1H. The simulation PVT condition is at typical corner case and 1.0 V supply voltage.

Table 3.2. Performance comparison with standard cells and HDCs.

Delay

The cell delay is the summation of high-to-low and low-to-high propagation delay, defined in equation (3-1). The area efficiency is an index of cost as (3-3), which is the delay comparison within same area. And, the energy efficiency means the inverse of transition power as (3-4). These two parameters can be regarded as a figure of merit to evaluate the performance of delay cells.

Area Delay Efficiency

Area = (3-3)

Energy Delay Efficiency

Energy = (3-4)

The normalization of area and energy efficiency is shown in Fig. 3.7 and Fig. 3.8, respectively.

By the simulation results, it is found that the HDCs of Rabaey and Dokic perform similar area and energy efficiency to the standard cells. But, the Sarawi architecture represents the best performance in both area and energy efficiency. That implies the Sarawi HDC can achieve the same delay by using the least area and energy compared with the other delay cells. So, we will re-analyze the Sarawi HDC in the following section and propose a new delay tunable and low power HDC for DCO resolution improvement.

Sarawi DEL2M1H Dokic DEL1M1H Rabaey BUFM2HDEL1M4HBUFM4H BUFM8H 0

10 20 30 40 50 60 70 80 90 100

Area Efficiency Normalization (%)

Fig. 3.7. Normalization of area efficiency with standard cells and HDCs.

Sarawi DEL2M1H Dokic DEL1M1HBUFM2H Rabaey DEL1M4HBUFM4H BUFM8H 0

10 20 30 40 50 60 70 80 90 100

Energy Efficiency Normalization (%)

Fig. 3.8. Normalization of energy efficiency with standard cells and HDCs.