Implementation

The proposed all-digital and cell-based 5 MHz PVT tolerance clock generator is implemented with UMC 90 nm technology. Fig. 4.11 summarizes the area distribution.

The PVT detector, mapper and clock oscillator occupy 89.81 %, 3.66 % and 6.52 % of overall area, respectively. The overall area is about 0.28 mm². Fig. 4.12 is the layout view of the proposed design. The non-blocked part in Fig. 4.12 is the other design integrated with our proposed PVT tolerance clock generator.

Fig. 4.11. Area distribution of PVT tolerance clock generator.

Fig. 4.12. Layout of the proposed PVT tolerance clock generator.

Table 4.1. Performance comparison of clock sources.

Process 90nm With 90nm

Oscillator Pad

Quartz Crystal) 2.25 1.6

Max. Frequency Error (%)

1.9 / 0.002

(FCL+DPR[2]) 0.005 0.004 2.6

Frequency Tunable Yes No No No

Table 4.1 lists the comparison among different clock generators. The proposed PVT tolerance clock generator has less power consumption and less area than quartz crystal oscillator [26], MEMS [12] and ring-oscillator-based design with calibration circuits [13]. By the means of frequency tuning capability from frequency calibration loop (FCL) and DFR [2], the proposed design has similar maximum frequency error to the quartz crystal oscillator [26] and MEMS [12] approaches. When the service time increases, the frequency tuning command provides immediate frequency calibration capability to avoid frequency drift. We can always fine-tune the frequency of clock generator to enhance and hold the clock frequency accuracy.

Moreover, theses two approaches, quartz crystal oscillator [26] and MEMS [12], have extra manufacturing costs and difficulties in system integration. The proposed design is all-digital and integrable with system under standard CMOS technology.

Though the ring-oscillator-based design [13] overcomes the PVT variations in 0.25 µm with calibration circuits, the design complexity for power minimization due to band-gap voltage regulator is the major challenge in deep sub-micron CMOS process.

4.5 Summary

For replacing the quartz crystal oscillator, we propose a new method to design a low power, small area and high integrated clock generator with frequency tunable capability to improve the frequency accuracy. The all-digital PVT tolerance clock generator is designed with all standard cells in UMC 90 nm technology. The frequency tolerance is 1.9 % under any PVT conditions without frequency tuning command. The frequency tuning command from frequency recovery loop can enhance the frequency accuracy performance to 0.002 %. The power is 343 µW under 1.0 V. To summarize, it is found that the proposed design achieves power and area reduction by 99.1 % and 99.5 % in comparison with the quartz crystal oscillator.

(a) (b)

Fig. 4.13. PVT tolerance clock generator comparison (a) power (b) area.

CHAPTER 5

Conclusion and Future Work

5.1 Conclusion

For wireless body area network applications, the reliability, portability and low cost are especially required. However, the ADC dominates the overall power consumption in receiver and the sampling clock frequency offset degrades the system PER performance. The all-digital PFTCG is proposed for ADC power reduction and PER performance improvement by the DPR and DFR [2]. The DPR estimates the sampling clock phase offset and directly adjusts the ADC sampling phase within the symbol rate instead of over-sampling. The DFR compensates the resulting phase error after FFT and directly tunes the ADC sampling frequency. Both methods prevent the received data from sampling clock phase and frequency interference with the aid of a PFTCG.

The proposed all-digital and cell-based PFTCG provides eight clock phases for phase selection and ±1072 ppm frequency tuning range centered at 5 MHz. The proposed design is measured with power 145.8 µW and 95.4 µW at 5 MHz under 1.0

V and 0.8 V in the standard process 90 nm CMOS technology. By both DPR and PFR, the ADC power reduction, considering the PFTCG, is about 46 %.

For further power reduction on the always-turned-on clock generator, we propose a new method to design a low power DCO by the HDC. Compared with standard cells, the proposed HDC can achieve the same delay with the least area and energy. Moreover, the proposed delay tunable HDC has 0.78 ps delay resolution with fine linearity and maintains the low power feature. As a result, at 5 MHz and 200 MHz, the HDC-based DCOs consume only 2.6 µW and 14.3 µW under 1.0 V supply, respectively. The power and area reductions in PFTCG are 73.0 % and 47.6 %.

For replacing the large power, large area and disintegrable quartz crystal oscillator, the PVT tolerance clock generator is designed. The proposed cell-based clock generator has 1.9 % frequency tolerance under any PVT conditions without frequency tuning command. The tuning command from frequency recovery loop can enhance the frequency accuracy performance to 0.002 %. The proposed PVT tolerance clock generator is implemented with 90 nm CMOS technology and the power consumption is 343 µW under 1.0 V. Compared with quartz crystal oscillator, we save the power and area by 99.1 % and 99.5 %, respectively.

In this thesis, we propose several designs to overcome the performance, power, area and cost challenge on clock generator for WBAN applications. The designs, including the all-digital PFTCG, low power HDC-based DCO and PVT tolerance clock generator, result in the high reliability, portability and robustness in WBAN systems. Consequently, the overall power and area reduction in WSN are 89.8 % and 88.1 %, respectively.

(a) (b)

Fig. 5.1. Overall comparison (a) power (b) area.

5.2 Future Work

In the future, the following work is to design a modified all-digital PFTCG with the proposed low power HDC-based DCO for saving more power consumption. Then, the proposed PVT tolerance clock generator is integrated with all-digital PFTCG as well. For further area and power reduction in PVT tolerance clock generator, the delay lines architecture in PVT detector can be replaced, and the HDC-based DCO can be also integrated in the clock oscillator for power saving.

Through these integrations, we can implement an ultra low power and low cost clock generator module with phase and frequency tunable capability, which can improve the reliability and provide the competitiveness in WBAN systems.

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研 究 成 果

研討會論文：

[1] M.-H. Yang, J.-Y. Yu, J.-T. Chen and C.-Y. Lee, “A Dynamic Phase-Frequency Recovery for Power Reduction in OFDM Systems,” International Symposium on VLSI Design, Automation and Test, pp.107-110, April 2007.

[2] J.-Y. Yu, J.-T. Chen, M.-H. Yang, C.-C. Chung and C.-Y. Lee, “An All-Digital Phase-Frequency Tunable Clock Generator for Wireless OFDM Communications Systems,” IEEE International SoC Conference, pp.305-308, Sep. 2007.

[3] J.-Y. Yu, C.-Y. Yu, S.-B. Huang, T.-W. Chen, J.-T. Chen, K.-L. Kuo and C.-Y. Lee,

“A 0.5V 4.85Mbps Dual-Mode Baseband Transceiver with Extended Frequency Calibration for Biotelemetry Applications,” Asian Solid-State Circuit Conference, Nov. 2008.

待審專利：

[1] 李鎮宜, 游瑞元, 陳俊廷, “數位遲滯線與其應用,” 中華民國專利申請案號 97127455, 97年7月18日。

[2] 李鎮宜, 游瑞元, 陳俊廷, 余建螢, “絕對延遲時間產生裝置,” 中華民國專利申 請案號97127581, 97年7月21日。