I MPLEMENTATION AND M EASUREMENT R ESULT OF T EST C HIP

CHAPTER 3 DESIGN OF 1.0MB 6T PIPELINE SRAM WITH THREE STEP-UP

3.7 I MPLEMENTATION AND M EASUREMENT R ESULT OF T EST C HIP

A 1.0Mb test chip is fabricated using UMC 40nm advanced Low-Standby-Power (LP) bulk CMOS technology. Fig. 3-37 shows the die photo.

Fig. 3-37 Die photo

Fig. 3-38 shows measured error free full functionality die yield (without redundancy) versus VDD (=VCC) for FF (58 dies), TT (65 dies), and SS (53 dies) corners (without read/write assist technique). At 0.7V, we still have die yield of about 70% (FF) and 30% (TT). The VMIN of this SRAM is limited by Write operation.

VDD(V)

0.3 0.6 0.9 1.2 1.5

Die Yield(%)

0 20 40 60 80 100

PFNF PTNT PSNS

Fig. 3-38 Measured error free full functionality die yield (without redundancy) versus VDD (=VCC) for FF (58 dies), TT (65 dies), and SS (53 dies) corners (without

read/write assist technique)

1.0Mb 6T SRAM

Fig. 3-39 shows with TSUWL and ADAWA technique. At 0.7V, we still have die yield of about 40% (FF) and 15% (TT). Fig. 3-40 shows with TSUWL and BLUD technique. At 0.7V, we still have die yield of about 60% (FF) and 20% (TT).

Fig. 3-39 Measured error free full functionality die yield (without redundancy) versus VDD (=VCC) for FF (58 dies), TT (65 dies), and SS (53 dies) corners (with

Fig. 3-40 Measured error free full functionality die yield (without redundancy) versus VDD (=VCC) for FF (58 dies), TT (65 dies), and SS (53 dies) corners (with

TSUWL and BLUD technique)

Fig. 3-41 Measured Bit Failure Rate (BFR) at TT corner (Write-Assist: TSUWL and ADAWA; Read-Assist: TSUWL and BLUD)

VDD (V)

Fig. 3-42 Measured Bit Failure Rate (BFR) at FF corner (Write-Assist: TSUWL and ADAWA; Read-Assist: TSUWL and BLUD)

73 VDD (V)

0.60 0.65 0.70 0.75 0.80

Bit Failure Rate (%)

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

No Technique

W/ Write-Assist Technique W/ Read-Assist Technique

Fig. 3-43 Measured Bit Failure Rate (BFR) at SS corner (Write-Assist: TSUWL and ADAWA; Read-Assist: TSUWL and BLUD)

Fig. 3-41 shows Bit Failure Rate (BFR) at TT corner (Write-Assist: TSUWL and ADAWA; Read-Assist: TSUWL and BLUD). When read/write operation with write-assist technique or read-assist technique, the BFR is better than no technique.

Fig. 3-42 shows Bit Failure Rate (BFR) at FF corner. Fig. 3-43 shows Bit Failure Rate (BFR) at SS corner. Fig.3-44 shows failure bit count improvement with TSUWL and Boosting WL technique at three corners which are TT, FF, and SS corner. Fig.3-45 shows failure bit count improvement with TSUWL and BLUD technique at three corners which are TT, FF, and SS corner.

74 VDD(V)

0.60 0.65 0.70 0.75 0.80 0.85

Failure Bit Count Improvement

Fig. 3-44 Measured Failure Bit Count Improvement with TSUWL and Boosting WL technique

VDD(V)

0.60 0.65 0.70 0.75 0.80 0.85

Failure Bit Count Improvement

Fig. 3-45 Measured Failure Bit Count Improvement with TSUWL and BLUD technique

Chapter 4 Conclusions

In this thesis, we presented a high-performance 1.0Mb 6T SRAM using 40nm Low Power (LP) 1P9M CMOS technology. Banking architecture, hierarchical WL, and hierarchical BL were used to improve the access performance. Large signal sensing for BLUD and TSUWL were utilized to mitigate Read-Disturb and Half-Selected Disturb while maintaining adequate sensing margin. AVD was used to mitigate gate dielectric over-stress with booster while maintaining adequate gate dielectric reliability. ADAWA was used to improve write ability while maintaining adequate WM and WSNM. The SRAM operated from 1.5V down to 0.6V. The operating frequency is [email protected].

Reference of Chapter 2

[2-1] Adel S. Sedra, Kenneth C. Smith, “Microelectronic Circuits” 5rd ed.

Oxford University Press, 2003.

[2-2] Ching-Te Chuang, S. Mukhopadhyay, Jae-Joon Kim, Keunwoo Kim, and R. Rao, “High-Performance SRAM in Nanoscale CMOS: Design Challenges and Techniques,” IEEE International Workshop on Memory Technology, Design and Testing, 2007, pp.4-12.

[2-3] T. Fischer, E. Amirante, P. Huber, T. Nirschl, A. Olbrich, M. Ostermayr, and D. Schmitt-Landsiedel, “Analysis of read current and write trip voltage variability from a 1-mb sram test structure,” IEEE Trans on Semiconductor Manufacturing, 2008, vol. 21, no.4, pp. 534–541.

[2-4] J. Wang, S. Nalam, and B.H. Calhoun, “Analyzing static and dynamic write margin for nanometer SRAMs,” IEEE International Symposium on Circuits and Systems, 2008, pp.129-134.

[2-6] Sridhar Ramalingam, Elakkumanan Praveen, Natarajan Sreedhar,

“Tutorial 6: Design Challenges and Solutions for Nanoscale Memories”, IEEE International Symposium on Circuits and Systems, 2007, nil28 - nil29

[2-6] S. H Dhong, O. Takahashi, M. White, T. Asano, T. Nakazato, J.

Silberman, A. Kawasumi, and H. Yoshihara, “A 4.8GHz fully pipelined embedded SRAM in the streaming processor of a CELL processor,”

IEEE International Solid-State Circuits Conference, 2005, pp.486-612.

[2-7] A. Bhavanagarwala, X. Tang, and J. Meindl, “The impact of intrinsic

device fluctuations on CMOS SRAM cell stability,” IEEE Journal of Solid State Circuits, Apr. 2001, vol. 36, no. 4, pp. 658-665.

[2-8] M. Yamaoka, and H. Onodera, “A Detailed Vth-Variation Analysis for Sub-100-nm Embedded SRAM Design,” IEEE International SOC Conference, 2006, pp.315-318.

[2-9] S. Ohbayashi, M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Imaoka, Y. Oda, T.

Yoshihara, M. Igarashi, M. Takeuchi, H. Kawashima, Y. Yamaguchi, K.

Tsukamoto, M. Inuishi, H. Makino, K. Ishibashi, and H. Shinohara, “A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits,” IEEE Journal of Solid-State Circuits , April 2007, vol.42, no.4, pp.820-829.

[2-10] J. Davis, D. Plass, P. Bunce, Y. Chan, A. Pelella, R. Joshi, A. Chen, W.

Huott, T. Knips, P. Patel, K. Lo, and E. Fluhr, “A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor,” IEEE International Solid-State Circuits Conference, 2006, pp.2564-2571.

[2-11] D. W. Plass, and Y. H. Chan, “IBM POWER6 SRAM arrays,” IBM Journal of Research and Development, Nov. 2007, vol.51, no.6,

pp.747-756.

[2-12] J. Pille, C. Adams, T. Christensen, S. Cottier, S. Ehrenreich, T. Kono, D.

Nelson, O. Takahashi, S. Tokito, O. Torreiter, O. Wagner, and D. Wendel,

“Implementation of the CELL Broadband Engine in a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V,” IEEE International Solid-State Circuits Conference, 2007, pp.322-606.

[2-13] J. Pille, C. Adams, T. Christensen, S. Cottier, S. Ehrenreich, T. Kono, D.

Nelson, O. Takahashi, S. Tokito, O. Torreiter, O. Wagner, and D. Wendel,

“Implementation of the Cell Broadband Engine™ in 65 nm SOI Technology Featuring Dual Power Supply SRAM Arrays Supporting 6 GHz at 1.3 V,” IEEE Journal of Solid-State Circuits, Jan. 2008, vol.43, no.1, pp.163-171.

[2-14] M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Ohbayashi, and Y. Nakase, H.

Shinohara, “A 45nm 0.6V cross-point 8T SRAM with negative biased read/write assist,” Symposium on VLSI Circuits, 2009, pp.158-159.

[2-15] A. Raychowdhury, B. Geuskens, J. Kulkarni, J. Tschanz, K. Bowman, T.

Karnik, Shih-Lien Lu, V. De, and M.M. Khellah, “PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction,” IEEE International Solid-State Circuits Conference, 2010, pp.352-353.

[2-16] K. Takeda, T. Saito, S. Asayama, Y. Aimoto, H. Kobatake, S. Ito, T.

Takahashi, K. Takeuchi, M. Nomura, and Y. Hayashi, “Multi-step word-line control technology in hierarchical cell architecture for scaled-down high-density SRAMs,” IEEE Symposium on VLSI Circuits, 2010, pp.101-102.

[2-17] K. Takeda, T. Saito, S. Asayama, Y. Aimoto, H. Kobatake, S. Ito, T.

Takahashi, K. Takeuchi, M. Nomura, and Y. Hayashi, “Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMs,” IEEE Journal of Solid-State Circuits, April 2011, vol.46, no.4, pp.806-814.

[2-18] H. Yamauchi, “A Discussion on SRAM Circuit Design Trend in Deeper Nanometer-Scale Technologies,” IEEE Transactions on Very Large Scale Integration Systems, May 2010, vol.18, no.5, pp.763-774.

[2-19] K. Nii, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, Y. Oda, K. Usui, T.

Kawamura, N. Tsuboi, T. Iwasaki, K. Hashimoto, H. Makino, and H.

Shinohara, “A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment,” IEEE Symposium on VLSI Circuits, 2008, pp.212-213.

[2-20] Y. Fujimura, O. Hirabayashi, T. Sasaki, A. Suzuki, A. Kawasumi, Y.

Takeyama, K. Kushida, G. Fukano, A. Katayama, Y. Niki, and T. Yabe,

“A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm2 cell in 32nm high-k metal-gate CMOS,” IEEE International Solid-State Circuits Conference, 2010, pp.348-349.

[2-21] H. Pilo, I. Arsovski, K. Batson, G. Braceras, J. Gabric, R. Houle, S.

Lamphier, F. Pavlik, A. Seferagic, Liang-Yu Chen, Shang-Bin Ko, and C.

Radens, “A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements”, IEEE International Solid-State Circuits Conference, 2011, pp.254-256.

[2-22] M. Khellah, Nam Sung Kim, J. Howard, G. Ruhl, Yibin Ye, J. Tschanz, D.

Somasekhar, N. Borkar, F. Hamzaoglu, G. Pandya, A. Farhang, K.

Zhang, V. De, “A 4.2GHz 0.3mm2 256kb Dual-V/sub cc/ SRAM Building Block in 65nm CMOS,” IEEE International Solid-State Circuits Conference, 2006, pp.2572-2581.

[2-23] Kim Keejong, H. Mahmoodi, K. Roy, “A Low-Power SRAM Using Bit-Line Charge-Recycling,” IEEE Journal of Solid-State Circuits, Feb.

2008, vol.43, no.2, pp.446-459.

[2-24] M. Alam and S. Mahapatra, “A comprehensive model of PMOS NBTI degradation,” Microelectron. Reliab., vol. 45, no. 1, pp. 71–81, 2005.

Reference of Chapter 3

[3-1] International Technology Roadmap for Semiconductors, ITRS, http://public.itrs.net

[3-2] Ching-Te Chuang, S. Mukhopadhyay, Jae-Joon Kim, Keunwoo Kim, and R. Rao, “High-Performance SRAM in Nanoscale CMOS: Design Challenges and Techniques,” IEEE International Workshop on Memory Technology, Design and Testing, 2007, pp.4-12.

[3-3] E. Josse, S. Parihar, O. Callen, P. Ferreira, C. Monget, A. Farcy, M.

Zaleski, D. Villanueva, R. Ranica, M. Bidaud, D. Barge, C. Laviron, N.

Auriac, C. Le Cam, S. Harrison, S.Warrick, F. Leverd, P. Gouraud, S.

Zoll, F. Guyader, E. Perrin, E. Baylac, J. Belledent, B. Icard, B.

Minghetti, S. Manakli, L. Pain, V. Huard, G. Ribes, K. Rochereau, S.

Bordez, C. Blanc, A. Margain, D. Delille, R. Pantel, K. Barla, N. Cave, and M. Haond, “A cost-effective low-power platform for the 45-nm technology node,” International Electron Devices Meeting, 2006, pp. 1–4.

[3-4] H. Fukutome, Y. Momiyama, T. Kubo, E. Yoshida, H. Morioka, M.

Tajima, and T. Aoyama, “Suppression of Poly-Gate-Induced Fluctuations in Carrier Profiles of Sub-50nm MOSFETs”, International Electron Devices Meeting, 2006, pp. 1–4.

[3-5] T. Hayashi, M. Mizutani, M. Inoue, J. Yugami, J. Tsuchimoto, M. Anma, S. Komori, K. Tsukamoto, Y. Tsukamoto, K. Nii, Y. Nishida, H. Sayama, T. Yamashita, H. Oda, T. Eimori, and Y. Ohji, “Vth-tunable CMIS platform with high-k gate dielectrics and variability effect for 45nm node,” International Electron Devices Meeting, 2005, pp. 906–909.

[3-6] Yi-Wei Lin, “A 55nm 6T SRAM with Variation-Tolerant Word-Line Under-Drive and Data-Aware Write-Assist,” master thesis of Department of Electronics Engineering of National Chiao Tung University, 2010.

[3-22] Chi-Shin Chang, “40nm 1.0Mb 6T Pipeline SRAM with Step-Up Word- Line and Adaptive-Data-Aware Write-Assist Design,” master thesis of Department of Electronics Engineering of National Chiao Tung University,

2011.

[3-7] S. Ohbayashi, M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Imaoka, Y. Oda, M.

Igarashi, M. Takeuchi, H. Kawashima, H. Makino, Y. Yamaguchi, K.

Tsukamoto, M. Inuishi, K. Ishibashi, and H. Shinohara, "A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits", Symposium on VLSI Circuits, 2006, pp.17-18.

[3-8] S. Ohbayashi, M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Imaoka, Y. Oda, T.

Yoshihara, M. Igarashi, M. Takeuchi, H. Kawashima, Y. Yamaguchi, K.

[3-9] M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Ohbayashi, S. Imaoka, H. Makino, Y. Yamagami, S. lshikura, T. Terano, T. Oashi, K. Hashimoto, A. Sebe, G.

Okazaki, K. Satomi, H. Akamatsu, H. Shinohara, “A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations,” IEEE International Solid-State Circuits Conference, 2007, pp.326-606.

[3-10] K. Nii, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, S. Imaoka, H. Makino, Y. Yamagami, S. Ishikura, T. Terano, T. Oashi, K. Hashimoto, A. Sebe, S.

Okazaki, K. Satomi, H. Akamatsu, and H. Shinohara, “A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations,” IEEE Journal of Solid-State Circuits, Jan.

2008, vol.43, no.1, pp.180-191.

[3-11] K. Takeda, T. Saito, S. Asayama, Y. Aimoto, H. Kobatake, S. Ito, T.

[3-12] K. Takeda, T. Saito, S. Asayama, Y. Aimoto, H. Kobatake, S. Ito, T.

[3-13] A. Kawasumi, T. Yabe, Y. Takeyama, O. Hirabayashi, K. Kushida, A.

Tohata, T. Sasaki, A. Katayama, G. Fukano, Y. Fujimura, and N. Otsuka,

“A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit-ÃŸ-ratio Memory Cell,” IEEE International Solid-State Circuits Conference, 2008, pp.382-622.

[3-14] K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N.

Vallepalli, Y. Wang, B. Zheng, and M. Bohr, “A 3-GHz 70Mb SRAM in 65nm CMOS Technology with Integrated Column-Based Dynamic Power Supply,” IEEE International Solid-State Circuits Conference, 2005, pp. 474-475.

[3-15] M. Yamaoka, N. Maeda, Y. Shinozaki, Y. Shimazaki, K. Nii, S. Shimada, K. Yanagisawa, and T. Kawahara, “Low-Power Embedded SRAM

Modules with Expanded Margins for Writing,” IEEE International Solid-State Circuits Conference, 2005, pp. 480-481.

[3-16] T. Suzuki, H. Yamauchi, Y. Yamagami, K. Satomi, H. Akamatsu, “A Stable SRAM Cell Design Against Simultaneously R/W Disturbed Accesses,” Symposium on VLSI Circuits, 2006, pp. 11-12.

[3-17] Meng-Fan Chang, Jui-Jen Wu, Kuang-Ting Chen, Hiroyuki Yamauchi,

“A Differential Data Aware Power-supplied (D2AP) 8T SRAM Cell with Expanded Write/Read Stabilities for Lower VDDmin Applications,”

Symposium on VLSI Circuits, 2009, pp. 156-157.

[3-18] Meng-Fan Chang, Jui-Jen Wu, Kuang-Ting Chen, Yung-Chi Chen, Yen-Hui Chen, R. Lee, Hung-Jen Liao, H. Yamauchi, “A Differential Data Aware Power-supplied (D2AP) 8T SRAM Cell with Expanded Write/Read Stabilities for Lower VDDmin Applications,” IEEE Journal of Solid-State Circuits, June 2010, vol.45, no.6, pp.1234-1245.

[3-19] Y. Fujimura, O. Hirabayashi, T. Sasaki, A. Suzuki, A. Kawasumi, Y.

Takeyama, K. Kushida, G. Fukano, A. Katayama, Y. Niki, and T. Yabe,

[3-20] H. Pilo, I. Arsovski, K. Batson, G. Braceras, J. Gabric, R. Houle, S.

Lamphier, F. Pavlik, A. Seferagic, Liang-Yu Chen, Shang-Bin Ko, and C.

[3-21] J. Pille, D. Wendel, O. Wagner, R. Sautter, W. Penth, T. Froehnel, S.

Buetter, O. Torreiter, M. Eckert, J. Paredes, D. Hrusecky, D. Ray, M.

Canada, “A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor,” IEEE International Solid-State Circuits Conference, 2010, pp.344-345.

[3-23] Kim Keejong, H. Mahmoodi, K. Roy, “A Low-Power SRAM Using Bit-Line Charge-Recycling,” IEEE Journal of Solid-State Circuits, Feb.

2008, vol.43, no.2, pp.446-459.

[3-24] Hao-I Yang, Yi-Wei Lin, Mao-Chih Hsia, Geng-Cing Lin, Chi-Shin Chang, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, and Chih-Chiang Hsu, “High-Performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with Adaptive BL Bleeder,” Proc. 2012 IEEE International Symposium on Circuits and Systems (ISCAS), Seoul, Korea, May 20-23, 2012, pp. 1831-1834.

[3-25] Yi-Wei Lin, Hao-I Yang, Geng-Cing Lin, Chi-Shin Chang, Ching-Te Chuang, Wei Hwang, Chia-Cheng Chen, Willis Shih, Huan-Shun Huang,

“A 55nm 0.55V 6T SRAM with Variation-Tolerant Dual-Tracking Word-Line Under-Drive and Data-Aware Write-Assist,” Proc. 2012 IEEE International Symposium on Low Power Electronics and Design (ISLPED), Redondo Beach, CA, USA, July 30 – August 1, 2012, pp.

79-84.

[3-26] Yi-Wei Lin, Ming-Chien Tsai, Hao-I Yang, Geng-Cing Lin, Shao-Cheng Wang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee and Wei-Chiang Shih, “An All-Digital Read Stability and Write Margin Characterization Scheme for CMOS 6T SRAM Array,”

2012 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 23-25, 2012

在文檔中 40奈米1.0Mb 6T管線化靜態隨機存取記憶體與三步階升壓型字元線和位元線降壓和適應性電壓偵測 (頁 80-0)