IF Frequency Response and Circuit Netlist

Table 6 IF Frequency Response

Specification IF 100MHz IF 200MHz IF 300MHz

Vdd 1.8 1.8 1.8

Table 6 shows the performances at IF@ 100, 200 and 300MHz. The difference is noise figure. When the IF is higher, the noise figure is lower. Figure 2-42 shows the elements values and the currents. Figure 2-43 to Figure 2-46 shows the amplitude and phase at the nodes which are net56s and net78s in Figure 2-42. And finally, we list the circuit netlist.

Figure 2-42 The Element Values and Currents

Figure 2-43 Signal’s Amplitude at net56s and net78s for RF@3GHz

Figure 2-44 Signal’s Phase at net56s and net78s for RF@3GHz

Figure 2-45 Signal’s Amplitude at net56s and net78s for RF@15GHz

Figure 2-46 Signal’s Phase at net56s and net78s for RF@15GHz

Netlist

**********CURRENT MIRROR**********

xxXM1 net1d net1d net1s net1s NMOS_RF WR=4e-06 LR=1.8e-07 NR=10 m=4 xxXM1dr net1d VBIAS2 GND RPLPOLY_RF W=5e-06 L=2e-05

xxXM1sr GND net1s GND RPLPOLY_RF W=5e-06 L=3e-05

xxXM2 net2d net1d net2s net2s NMOS_RF WR=4e-06 LR=1.8e-07 NR=10 m=4 xxXM2sr GND net2s GND RPLPOLY_RF W=5e-06 L=3e-05

**********MATCHING NETWORK**********

xxX_in2l net4g INPUT GND SPIRAL_STD W=1.5e-05 S=2e-06 NR=1.5 RAD=3e-05 LAY=6 xxX_in2c net4g netr2 GND MIMCAP_WOS LT=3e-05 WT=3e-05 m=2

xxX_in2r netr2 GND GND RPHPOLY_RF W=5e-06 L=2e-06 m=2

xxX_lo2r GND netlor2 GND RPHPOLY_RF W=5e-06 L=2e-06 m=3

xxX_lo2c net58g netlor2 GND MIMCAP_WOS LT=2.4e-05 WT=2.4e-05 m=4

xxX_loL4 net58g LO GND SPIRAL_STD W=1.5e-05 S=2e-06 NR=1.5 RAD=3e-05 LAY=6 xxX_lo22r GND netlor22 GND RPHPOLY_RF W=5e-06 L=2e-06 m=3

xxX_lo22c net67g netlor22 GND MIMCAP_WOS LT=2.4e-05 WT=2.4e-05 m=4

xxX_loL2 net67g LO2 GND SPIRAL_STD W=1.5e-05 S=2e-06 NR=1.5 RAD=3e-05 LAY=6

**********TRANSCONDUCTANCE STAGE**********

xxXM4 net78s net4g net4s net4s NMOS_RF WR=4e-06 LR=1.8e-07 NR=16 xxXM4gr net4g VBIAS2 GND RPHPOLY_RF W=1e-06 L=1.2e-05

xxXM4sc net4s net2d GND MIMCAP_WOS LT=3e-05 WT=3e-05 m=4 xxXM4sr net4s net2d GND RPLPOLY_RF W=5e-06 L=5e-06

xxXM3 net56s net3g net3s net3s NMOS_RF WR=4e-06 LR=1.8e-07 NR=16 xxXM3gr net3g VBIAS2 GND RPHPOLY_RF W=1e-06 L=1.2e-05

xxXM3sc net3s net2d GND MIMCAP_WOS LT=3e-05 WT=3e-05 m=4 xxXM3sr net3s net2d GND RPLPOLY_RF W=5e-06 L=5e-06

xxXM3gc net3g GND GND MIMCAP_WOS LT=3e-05 WT=3e-05 m=4

**********LOAD**********

xxXM5gr VBIAS net58g GND RPHPOLY_RF W=1e-06 L=1.2e-05 xxXMbias1r VBIAS net67g GND RPHPOLY_RF W=1e-06 L=1.2e-05 xxXM5dr net57d VDD GND RPHPOLY_RF W=1e-06 L=4e-06

xxXM8dr net68d VDD GND RPHPOLY_RF W=1e-06 L=4e-06

**********SWITCHING STAGE**********

xxXM6 net68d net67g net56s net56s NMOS_RF WR=4e-06 LR=1.8e-07 NR=4 xxXM5 net57d net58g net56s net56s NMOS_RF WR=4e-06 LR=1.8e-07 NR=4 xxXM7 net57d net67g net78s net78s NMOS_RF WR=4e-06 LR=1.8e-07 NR=4 xxXM8 net68d net58g net78s net78s NMOS_RF WR=4e-06 LR=1.8e-07 NR=4

**********CURRENT BLEEDING**********

xxXMf8 net78s net78s netmr1 netmr1 PMOS_RF WR=5e-06 LR=1.8e-07 NR=20 m=2 xxXMmr1 netmr1 VDD GND RPHPOLY_RF W=3.7e-06 L=2e-06

xxXMf5 net56s net56s netmr2 netmr2 PMOS_RF WR=5e-06 LR=1.8e-07 NR=20 m=2 xxXMmr2 netmr2 VDD GND RPHPOLY_RF W=3.7e-06 L=2e-06

**********BUFFER**********

xxXMb2 VDD net57d IFP_PAD IFP_PAD NMOS_RF WR=5e-06 LR=1.8e-07 NR=20 m=4 xxXMbr2 GND IFP_PAD GND RPHPOLY_RF W=3e-06 L=4.8e-06 m=2

xxXMb VDD net68d IFN_PAD IFN_PAD NMOS_RF WR=5e-06 LR=1.8e-07 NR=20 m=4 xxXMbr1 GND IFN_PAD GND RPHPOLY_RF W=3e-06 L=4.8e-06 m=2

Chapter 3

C ONCLUSIONS A ^ND F ^UTURE P ^ROSPECTS

3.1

A low power double balanced mixer with differential-ended LO inputs topology for multiband UWB system is presented in this report. The double balanced mixer with differential-ended LO inputs structure can decrease the DC offset, compared to the double balanced mixer with single LO input. The double balanced mixer with differential-ended LO inputs is suitable for the low power, because LO-to-RF isolation can be increased with the topology. Experimental results of the proposed mixer show some disagreements with the simulation results for multiband operation from 3.1 GHz to 15 GHz range. Especially, the conversion gain isn’t as flat as simulation. The conversion voltage gain is from 6.1 ~ -0.7 dB.

Although RF return loss is also influenced, it still can be maintained better than 10 dB. The LO return loss is better than 14 dB. In linearity, there is still opportunity to improve the linearity by adding other circuit. The P1dB is -15 ~ -13 dBm from 4 GHz to 10 GHz. The IIP3 is 1 ~ 3 dBm from 4GHz to 10GHz.

In section 2.4.2, the re-simulations of modify show that the re-simulation results can approach the measurement results. The lower power consumption (17.5mW) and parasitic effects are added to the considerations of the re-simulation. Therefore the re-simulation shows that the power consumption and parasitic effects could be the elements of mismatch between simulation and measurement very much.

3.2

In conclusions, the power consumption and parasitic effect influence the circuit performances. How to maintain these factors between simulation and implementation is very important. Therefore, bias circuit can be integrated into the ultra-wideband mixer in future tape out to ensure that the performances aren’t influenced by process condition.

Furthermore, we must base on accurate models and careful simulation to make the measurement would close to the simulation. And the high frequency applications are the tendency. From the experiences of designing the UWB mixer, the parasitic effect is very important. However the EDA tool that we use now just can extract the resistances and capacitors. When the operation frequency is higher, the parasitic effect of inductor isn’t ignored. Therefore a more accurate and efficient EDA tool for extracting parasitic effect is quietly important.

R

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