5. Evaluation and Discussion
5.3 Impact of BCEC/WCEC (α) ratio
We set α to 0.5 and 0.8, and repeated simulations for these two types of CPUs. In Intel PXA255, as show in Fig. 5 and Fig. 6, OSRC can reduce 5.7% and 2.9% energy consumption in average (upper bound: 11.5% and 8.9%), respectively; the values in PACE are 2.1% and 1.0%. In Intel PXA270, as shown in Fig. 7 and Fig. 8, OSRC can reduce 13.4% and 6.7% energy consumption in average (upper bound: 17.3% and 13.3%), respectively; the values in PACE are 4.4% and 2.0%. These results show that when we set α to 0.5, the impacts of energy reduction are small for both types of CPU.
But when we raised α to 0.8, the optimal schedules are close to the WCE-stretch scheme, especially in 3 levels CPU. Because low slack time limits the aggressive frequency/voltage reduction in the optimal schedule, it happens in all offline DVS schedules.
24 0.7
0.8 0.9 1 1.1
1 1.2 1.4 1.6 1.8 2
AET/WCE
Expected energy consumption w.r.t. WCE-stretch
OSRC PACE LB
Fig. 5. The impact of
α
on expected energy consumption in PXA255 (α
=0.5).0.7 0.8 0.9 1 1.1
1 1.2 1.4 1.6 1.8 2
AET/WCET
Expected energy consumption w.r.t. WCE-stretch
OSRC PACE LB
Fig. 6. The impact of
α
on expected energy consumption in PXA255 (α
=0.8).0.7 0.8 0.9 1 1.1
1 2 3 4 5 6
AET/WCE
Expected energy consumption w.r.t. WCE-stretch
OSRC PACE LB
Fig. 7. The impact of
α
on expected energy consumption in PXA270 (α
=0.5).0.7 0.8 0.9 1 1.1
1 2 3 4 5 6
AET/WCE
Expected energy consumption w.r.t. WCE-stretch
OSRC PACE LB
Fig. 8. The impact of
α
on expected energy consumption in PXA270 (α
=0.8).The average energy saving percentage with respect to WCE-stretch for each scheme in Fig. 3 through Fig. 8 is denoted as (1－ average of expected energy with respect to WCE-stretch). The results are summarized in Table 5, and the proposed
26
OSRC is three times in average better than that of PACE for realistic CPUs.
Table 5：Average energy saving percentage with respect to WCE-stretch Figure OSRC PACE LB
Fig. 3 6.5% 2.0% 10.8%
Fig. 4 15.9% 5.6% 19.2%
Fig. 5 5.7% 2.1% 11.5%
Fig. 6 2.9% 1.0% 8.9%
Fig. 7 13.4% 4.4% 17.3%
Fig. 8 6.7% 2.0% 13.3%
Chapter 6
Conclusions and Future Work
6.1 Concluding Remarks
In this thesis, we have derived an optimal speed schedule for ideal CPUs for hard real-time systems by the Lagrange multiplier procedure, in a simple and elegant way, compared to PACE [2]. Because of limited available frequency/voltage levels in realistic CPUs, the optimal speed schedule for ideal CPUs can not be applied to realistic CPUs directly. To find an optimal speed schedule for realistic CPUs, we transform the original nonlinear programming problem into MKP based on the frequency/voltage levels and power consumption of a realistic CPU. With limited CPU frequency/voltage levels, the problem can be solved by the OSRC procedure feasibly. To evaluate the merits of the proposed OSRC, the actual data of Intel PXA255 and PXA270 CPU were used in the analysis. We have the following remarks.
First, the analysis results have shown that the poor energy saving by using PACE in realistic CPUs, which is almost the same as that in WCE-stretch. By using the OSRC for realistic CPUs, the results are very close to the low bound derived from an oracle algorithm. Secondly, we observed that the CPU frequency/voltage levels affect the energy efficiency of the optimal speed schedule in the stochastic DVS model: the more the levels, the more the energy saving. Thirdly, we found that compiler-assisted intra-task DVS algorithms are hard to collaborate with inter-task DVS algorithms if the frequency/voltage scaling code is inserted in the source code. Lastly, under the
28
stochastic DVS model, our scheme can provide the best solution for realistic CPUs using dynamic programming. Evaluation have shown that the energy saving of OSRC is three times in average better than that of PACE in Realistic CPUs.
6.2 Future Work
In stochastic DVS intra-task DVS algorithms, the speed schedule is only calculated once for different AET so that it is easy to work with most of inter-task DVS algorithms. But there still exists some unresolved issues in OSRC. First, all of the approaches addressed in this thesis neglect the time and energy consumption owing to frequency/voltage transitions. If the time of transitions takes too long, a task may miss the deadline. If the energy consumption due to transitions is too much, it reduces the energy saving efficiency. It may even wastes more energy than a non-DVS speed schedule in the worst case. Secondly, if a task has been preempted and then rescheduled, the pre-calculated optimal speed schedule may fail because the AET of the task may become different. These problems deserve for further investigation.
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