Implementation of M-AES Scheme

The implementation of M-AES can be easily done with already designed circuit components of CDR and requires no more new circuits. The implementation is shown in Fig. 4. 14. We incorporate the interpolators that are used in CDR and slightly modified them to perform fixed ratio interpolations. An interpolator in CDR was designed to interpolate 16-phases out of the two input phases; but now it is modified to interpolate 2-phases only, which is centered to the midpoint of two input phases but with different deviation quantities. For example, CDR interpolators produce phase0 to

phase15; but AES interpolators produce only phase pairs like phase7-8, phase6-9, phase5-10, phase4-11, and phase3-12. The multiple fixed ratio interpolations produce the alternating edge sampling all centered at the same mid-point, and the AES control signal becomes very easily implemented.

The AES circuit is composed of buffer, delay and interpolators to create altering phases. The P0~P9 phases from CDR circuit is sent to the AES circuit and divided into two groups. The even numbered phases are the edge sampling that needs to be alternating; and the odd numbered phases are the data sampling that shouldn’t be altered. Therefore the interpolators in the edge sampling are controllable by AES control signal and each of them generates different amount of alternation; while the interpolators in the data sampling are fixed and only interpolates the mid-point phases.

The simulated eye diagram of M-AES is shown in Fig.  4.  15. The waveforms are symmetric to the original sampling point.

However, it should be noted that in order for M-AES to function correctly, the majority vote in the pre-filter block of CDR should be skipped. Otherwise the M-AES will transform into a deadzone of +/- 0.08UI in phase tracking. The deadzone behavior is similar to traditional 3X oversampling, therefore the performance will be better than traditional 2X oversampling, but not as good as M-AES.

  (a) 

(b) 

Fig. 4. 14 (a) AES Edge sampling (b) Data sampling 

3.2 3.5 3.6 3.4 7.3 7.5 3.4 3.3 2.9 2.8

1UI=166.7ps

(ps)

(UI) 0.02 0.02 0.02 0.02 0.04 0.04 0.02 0.02 0.02 0.02

Fig. 4. 15 Simulation of AES 

Chapter 5

Experimental Results

5.1 Design flow and methodology

Fig. 5. 1 shows the design flow of the CDR circuit. The behavioral model is built and simulated using MATLAB, then the circuit is divided into analog and digital components. The analog and digital parts are modeled in SPICE and verilog respectively. Then the Nanosim mixed-signal simulator is used to verify the total behavior. Then analog circuit layout is simulated using SPICE, and digital synthesis and placement and route is done and simulated. After layout integration of the two, the circuit is again simulated using mixed-signal simulator. Finally the circuit is integrated and tape-out.

Fig. 5. 1 The design and implement flow of CDR. 

5.2 Layout

The CDR circuits together with a spread-spectrum clock generator and a continuous-time equalizer is implemented in UMC 90nm 1P9M process. The chip area is 1.25 X 1.1 (mm²) including 73 bonding pads. The layout floor plan and pad assignment are shown in Fig. 5. 2 and Table 5. 1. The multi-phase signals from PLL to the phase selection block and M-AES block must be routed symmetrically to ensure correct signal timing. Decoupling capacitors for supply and bias points are placed wherever possible, but needs to avoid high speed signal lines. The control signals from digital control to phase selection block and M-AES are very dense and needs extra caution in layout. The high speed I/O signal of this chip uses GSGSG probe for better signal integrity (shown in Table 5. 1), therefore pad 1~10, 54~73 are used for 6 GSGSG differential signals.

Fig. 5. 2 Layout view of test chip. 

Table 5. 1 The pad assignment of test chip.

Pad Function

1,2,5,6,9,10,54,55,58,59,62,63,64,

Ground 65,68,69,72,73

High-Speed Input / Output (using GSGSG)

3,7 Equalizer output

4,8

To reduce area, the GSGSG pads are placed interleaved and is used only 2 groups at a time, one at left side and the other at upper side. Therefore the equalizer, CDR and SSCG can be tested only one of them at a time.

5.3 Measurement Considerations

The testing environment setup is shown in Fig. 5. 3. All DC supply sources are given from Keithley 2400 Source Meter. Agilent N4903A Serial J-BERT provides the jittery and spread spectrum clock receiver data for CDR testing. It also provides the reference clock for PLL in spread spectrum clock generator. In order to measure BER, we use a BIST in the test chip that generates a waveform whose duty cycle is proportional to the accumulated error bits. This signal is the Error Signal. Tektronics TDS6124C Digital Storage Oscilloscope is used to measure the waveform of Error

39,40

Control signal & Low-Speed Input / Output

38 PLL Reference

Signal. Tektronics TDS6124C Digital Storage Oscilloscope also measures the waveform and jitter of CDR recovered clock and recovered data. Agilent E4440A Spectrum Analyzer is used to measure the spectrum of CDR recovered clock and the output result of spread spectrum clock generator.

Fig. 5. 3 Test Environment Setup   

Chapter 6

Conclusions and Future Works

6.1 Conclusions

A 6Gbps CDR with Multiple Alternating Edge Sampling for Spread Spectrum Clock is proposed. The CDR conforms to SATA generation 3 specifications. The CDR is a dual loop architecture that is suitable for multi-channel integration without the need of extra PLLs for different channels. The 2^nd-order digitally implemented phase tracking algorithm is programmable for different jitter conditions and can track spread spectrum clock transmission. The proposed Multiple Alternating Edge Sampling technique eradicates the unwanted side effects of binary phase detection and enhance the performance in severe ISI conditions. The CDR meets the specification of jitter quantity and spread spectrum clock of SATA-III and the specification of jitter tolerance mask of SDH STM-64 interface. The CDR is implemented in UMC 1P8M 90nm 1.0V Regular-Vt CMOS technology.

Table 6. 1 Comparison with recent works 

Process 90nm CMOS

(1.0V supply) 0.18um CMOS

(1.4V supply) 0.18um CMOS

(1.8V supply) 90nm CMOS 0.11um CMOS

(1.5V supply) 0.18um CMOS (1.8V supply)

Speed 6 Gb/s 0.2~4Gb/s 0.622~

3.125Gb/s 8~28Gb/s 10.8Gb/s 2.5~11.5Gb/s

Power 55mW 14mW(2Gb/s) 80mW 172mW 220mW 158mW

Active Area 0.78(mm²)

Freq Tolerance 1000 ppm 250ppm 200ppm 112ppm 400ppm 200ppm

SSC Tracking +/- 10000 ppm

The research of CDR is thriving and many new designs and ideas are being proposed. There are many potential improvements that may be incorporated in our CDR circuits, too. First, we may adopt a phase detector that counts the data transition and normalize its output with respect to data transition counts. The PD output is therefore independent from transition density, then the majority vote can be omitted to increase speed and recover M-AES behavior. Second, the M-AES is a promising technology that may improve BER performance in various jitter conditions. We may incorporate a feedback loop system for the M-AES and control the alternating phases according to the jitter condition. In this way we can adapt more severe jittery signals like ISI or channel attenuation. Third, as the fabrication process improves, the digital circuit latency can be greatly reduced. Therefore the loop delay is shortened and the jitter tracking ability and stability can be both improved. The input jitter mask can be easily met. Fourth, the phase interpolator may adopt finer resolution and use a compensation method that further increases the linearity. The cycle-to-cycle jitter of

recovered clock can then be reduced.

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