Chapter 4 Implementation and Verification
4.6 Implementation results
The maximum clock rate is 164MHz, which throughput can approach 655MHz at maximum. The PAR process of layout is applied with SYNOPSYS ASTRO by UMC 0.18 μm. The chip feature shows in table 4.6, and fig. 4.13 depicts the macro layout view of equalizer.
Table 4.6 – Chip feature
Module name equalizer
Technique 0.18um CMOS, 1P6M
Gate count 88390
Macro Size 1470x1470
Clock rate 528MHz
Throughput 480Mbit/s
Power dissipation 69.3826 mW
Figure 4.13 – Macro layout view
Chapter 5.
Simulation result and performance analysis
5.1. Introduction
In this chapter we will discuss the design flow, system platform and performance for the proposed design. In this study, behavior model is built by Matlab, and then do system co-simulation with RF in Agilent ADS tool. The design flow is illustrated in Fig. 5.1. this kind of waterfall model can work well up to 100k gate count design.
After RTL code is development and verified, two ways are used for implement the design, one is ASIC, the other is FPGA prototyping. Both of them will be discussed in chapter 5. FPGA prototyping is for verifying hardware design in general, because FPGA can simulate the real world situations which we don’t concern before.
After that, we synthesis the design to gate-level netlist by reasonable design constrains, and check the timing, area and power, if all of them pass, we will run
Place & Route. After all, we check the timing, area and power again. If all of them conformed, the design is done.
Figure 5.1 – Design & verification flow
5.2. System platform
MUX MUX
Figure 5.2 – System platform for UWB system
Our system is illustrated in Fig. 5.2 [5]. The platform by MATLAB is based on 802.15.3a standard. The system platform it built for system performance analysis and function verification. Such as error vector magnitude (EVM), bit error rate (BER) and packet error rate (PER).
In system co-simulation, the baseband platform and the RF behavior model are combined together in Agilent ADS tool. It is because the information of RF simulation is viewed as timed sequence, so the sequences calculated by MATLAB should be packed and transformed into timed sequence, then RF team can check their parameter settings and performance, such as Tx EVM, Tx power spectrum, Rx sensitivity and PER etc. Fig. 5.3 shows the co-simulation platform.
Figure 5.3 – Co-simulation platform
5.3. Performance analysis
The proposed channel is simulated in the IEEE 802.15.3a system platform. The PER analysis will focus on the 8% PER, which is requirement in IEEE 802.15.3a.
5.3.1 CE error tracking Performance
To analyze the CE error tracking performance of the proposed channel equalizer, error vector magnitude (EVM) is measured. The EVM value of CE can be derived as equ. 5.1, where yl,k is the data after equalization, xl,k is the data from transmitter, which means ideal vector.
From the definition, if the EVMdB is lower when system performance is better, the fig. 5.4 shows the EVM with and without CE error tracking in condition of CM2 channel model, 40ppm CFO, 40ppm SCO.
11 11.5 12 12.5 13 13.5 14 14.5 15 15.5 16
200Mbits/s, CM4, 40ppm CFO, 40ppm SCO
with CE error tracking without CE error tracking
Figure 5.4 – CE error tracking performance analysis
From the figure we can know, the proposed CE error tracking achieves 0.5~1dB gain in EVM compared with the system without CE error tracking.
To analysis the performance, packet error rate (PER) is also a target to achieve.
In IEEE 802.15.3a specification, PER is define as the probability of a 1024 byte packet miss, and should be less than 8%. The simulation of PER should be averaged
over a minimum of 50,000 realizations for each multi-path channel environment. The fig 5.5 shows the PER with and without CE error tracking. Notice that it achieves about 0.7 dB gain in PER compared with system without CE error tracking. The condition of the simulation is 200Mbits/s, CM4 channel and AWGN, 40ppm CFO and 40ppm SCO.
Figure 5.5 – CE error tracking performance analysis
5.3.2 Phase error tracking Performance
To verify the PET performance, the design is simulated under 40ppm CFO and 40ppm SCO, which is standard requirement. In the following simulation and
11 11.5 12 12.5 13 13.5 14 14.5 15 15.5 16
100 101 102
SNR [dB]
Packet Error Rate
200Mb/s, CM4, no CE error tracking 200Mb/s, CM4, with CE error tracking PER = 8%
comparison, the proposed design is compare to a simple PET algorithm, which realize
The algorithm only use 12 pilot subcarriers to against the phase offset, so the θ)l and φˆ will be oscillate, just like the fig. 5.6 shows. The fig. 5.7 shows the EVM l comparison between adaptive PET and without adaptive PET. PET with adaptive filter can against the noise. The fig. 5.7 is another PET performance analysis with EVM.
The figure shows that adaptive PET achieves 2.5 dB gains than other one. It increase the system performance a lot.
50 100 150 200 250 300 350 400 450 500 -0.4
-0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4
OFDM symbol #
phase offset tracking error
53.3Mbits/s, AWGN, 40ppm SCO, 40ppm CFO
with adaptive PET without adaptive PET
Figure 5.6 – The phase offset deviation analysis
11 11.5 12 12.5 13 13.5 14 14.5 15 15.5 16
-7.5 -7 -6.5 -6 -5.5 -5 -4.5 -4 -3.5 -3
SNR [dB]
EVM [dB]
200Mbits/s, CM4, CFO=40ppm, SCO=40ppm
with adaptive PET without adaptive PET
Figure 5.7 – PET performance analysis
5.3.3 System Performance
To verify the complete system performance of the proposed channel equalizer, PER of a complete IEEE802.15.3a basdband processor are measured with the Intel proposed indoor wireless channel model that contains 40ppm CFO and 40ppm SCO.
The PER curves of different transmission mode are shown in fig. 5.8.
The design SNR for 8% PER is listed in table 5.1. the table tells the proposed system has better performance in data rate of 480Mbits/s. The proposed baseband system achieves 1.05~6.09 dB gain in SNR compared with standard requirement.
Figure 5.8 – PER performance of the proposed baseband platform
2 4 6 8 10 12 14 16 18 20
10-2 10-1 100 101 102
SNR[dB]
Packet Error Rate
200Mb/s AWGN channel 480Mb/s AWGN channel 200Mb/s CM4+AWGN channel 480Mb/s CM2+AWGN channel PER = 8%
Table 5.1 – Required SNR for 8% PER of the proposed baseband platform
Data Rate
Design SNR (AWGN)
Design SNR (Multi-Path)
200Mbits/sec 4.11 dB 14.18 dB
480Mbits/sec 5.03 dB 15.01 dB
Data Rate
SNR Constraint (AWGN)
SNR Constraint (Multi-Path)
200Mbits/sec 5.16 dB 15.1 dB
480Mbits/sec 9.66 dB 21.1 dB
Chapter6.
Conclusions and Future Work.
6.1. Conclusions
Ultra Wide-Band uses OFDM system, which makes ultra wide-band system transmit in high data rates, but the system becomes sensitive to phase offset and phase noise. In this thesis, we propose a high speed and low complexity equalizer for WLAN IEEE 802.15.3a. In the proposed equalizer architecture, CORDIC module reduces the computation complexity of channel estimation, equalization, and phase error tracking.
IP qualification is the key of SOC, as SOC become more and more popular, IP qualification become more and more important. In this study, we consider the equalizer with soft IP qualification to achieve IP reuse.
6.2. Future Work
In the proposed equalizer architecture, CORDIC module reduces the computation complexity of channel estimation, equalization, and phase error tracking,
but it cost too much area. In the proposed design, CORDIC and de-CORDIC use about 50% of the total gate count of the equalizer. If there is more than one block need CORDIC module (like CORDIC based FFT [14]), then CORDIC can be share and reuse.
Bibliography
[1] A. Batra, et al., “MultiBand OFDM Physical Layer Proposal for IEEE 802.15 Task Group 3a,”, http://www.multibandofdm.org, September 2004.
[2] A.Saleh and R.Valenzuela, “A Statistical Model for Indoor Multipath Propagation,”, IEEE JSAC, Vol. SAC-5, No. 2, pp. 128-137, Feb. 1987
[3] IEEE P802.15-02/279r0-SG3a, “UWB Channel Modeling Contribution from Intel”, available at http://grouper.ieee.org/groups/802/15/pub/2002/Jul02.
[4] J. Foerster et al., "Channel modeling sub-committee report final,", IEEE P802.15 Working Group for Wireless Personal Area Networks (WPANs), IEEE P802.15-02/490r1-SG3a, Feb. 2003.
[5] Anuj Batra, Jaiganesh Balakrishnan, G. Roberto Aiello, Jeffrey R. Foerster, and Anand Dabak, , “Design of a Multiband OFDM System for Realistic UWB Channel Environments”, IEEE TRANSACTIONS ON MICROWAVE THEORY
AND TECHNIQUES, VOL. 52, NO. 9, SEPTEMBER 2004
[6] Chia-Sheng Peng; Yuan-Shin Chuang; Kuei-Ann Wen, “CORDIC-based architecture with channel state information for OFDM baseband receiver”, IEEE
Transactions on Consumer Electronics, Volume 51, Issue 2, pp. 403 – 412, May 2005
[7] Yi-Hsin Yu, “A channel equalizer for OFDM-based wireless access system“, M.S.
thesis, Dept. Electronics Engineering, National Chiao Tung Univ., Taiwan, 2004.
[8] Yuqiang Zhang; Junhui Zhao, “Performance simulation of fixed-point for MB-OFDM UWB system”, Wireless Communications, Networking and Mobile
Computing, 2005. Proceedings. 2005 International Conference on Volume 1, pp.
292 - 295, Sept. 2005
[9] Anuj Batra, Jaiganesh Balakrishnan, G. Roberto Aiello, Jeffrey R. Foerster, and Anand Dabak, , “Design of a Multiband OFDM System for Realistic UWB Channel Environments”, IEEE TRANSACTIONS ON MICROWAVE THEORY
AND TECHNIQUES, VOL. 52, NO. 9, SEPTEMBER 2004
[10] Yuan-Mao Chang; Cheng-Wei Kuang; Chien-Ching Lin; Tzu-Shien Sang;
Hsie-Chia Chang; Chen-Yi Lee, “A new channel equalizer for OFDM-based wireless communications”, IEEE VLSI-TSA International Symposium pp.104 –
107, April 2005
[11] Choi, J.D.; Stark, W.E., “Performance of UWB communications with imperfect channel estimation”, Military Communications Conference, 2003. MILCOM
2003. IEEE Vol 2, pp. 915 - 920 Vol.2, Oct. 2003.
[12] Hewavithana, T.C.; Brookes, D.A., “Blind adaptive channel equalization for OFDM using the cyclic prefix data”, Global Telecommunications Conference,
2004. GLOBECOM '04. IEEE Volume 4, pp.2376 - 2380 Vol.4, Dec. 2004
[13] Hsuan-Yu Liu; Chien-Ching Lin; Yu-Wei Lin; Ching-Che Chung; Kai-Li Lin;
Wei-Che Chang; Lin-Hung Chen; Hsie-Chia Chang; Chen-Yi Lee, “A 480Mb/s LDPC-COFDM-based UWB baseband transceiver”, Proceedings on of IEEE
International Solid-State Circuits Conference, pp. 444 - 609, Feb. 2005
[14] Jen-Chih Kuo; Ching-Hua Wen; An-Yeu Wu, “Implementation of a programmable 64/spl sim/2048-point FFT/IFFT processor for OFDM-based
communication systems”, Circuits and Systems, 2003. ISCAS '03. Proceedings
of the 2003 International Symposium, pp. II-121 - II-124 vol.2, May 2003.
簡 歷
姓名 : 張懷仁 性別 : 男 籍貫 : 雲林縣
生日 : 民國七十一年九月一號
地址 : 嘉義市西區福民里福州二街 46 號
學歷 : 國立交通大學電子工程研究所碩士班 93/09~95/06 國立暨南大學電機工程學系 89/09~93/06 協同私立高級中學 86/09~89/06
論文題目 : CORDIC based Equalizer for Ultra-Wide band system 用於 UWB 之 CORDIC based 等化器設計