Sampling Clock Offset Tracking

t

Where T_t and T_r are the sampling period at transmitter and receiver, respectively.

The effect on received signal after DFT can be shown as

) function of symbol index l and sub-channel index k, as fig. 3.18 shows.

Figure 3.18 – Phase offset due to SCO

Two long preambles can help us to estimation the SCO offset and compensate for it. The estimation of φ can be expressed as follow ~₀

 value. The tracking algorithm of φ~_l

proposed here can be written as

l

Where ε is adaptive constant for SCO, P_l,k are desired signals that specified.

Chapter 4.

Implementation and Verification

4.1. Architecture of the proposed equalizer.

By using the equalizer scheme as described in chapter 3, we will discuss the implementation of equalizer. Fig. 4.1 shows the function block of the proposed equalizer.

Figure 4.1 – function block of the processed equalizer.

4.1.1. Architecture of the CORDIC based Equalizer.

The architecture of the proposed channel equalizer is illustrated in fig. 4.2. In the proposed design, the architecture spilt into two parts, one is phase, the other one is magnitude. The magnitude part is simply implemented as a divider with 5 clock latency. The phase part is much complexity and will be discuss in the follow section.

Channel estimation

Figure 4.2 - The architecture of the proposed equalizer

4.1.1.1 Architecture of RAM control

(a) (b)

Figure 4.3 – RAM control module (a) Architecture, (b) finite state machine

Fig. 4.3 illustrated the architecture of the proposed RAM control. The function of RAM control module is to store the channel frequency response (CFR) in the memory. When the first preamble arrived, it will be stored in memory. When the second preamble is arrived, both preambles will send to the “channel estimation”

block, then the estimated channel will be calculated and store in CFR memory.

4.1.1.2 Architecture of CE & PET (phase)

θ)l

φ~l θ)l

φ~l

θ)0 0

φ~

CE

Equalization

(a) (b)

Figure 4.4 – CE & PET module (a) Architecture, (b) finite state machine

Fig. 4.4 illustrated the architecture of the CE & PET module, the module is a finite state machine with two states. In CE state, channel is estimated and phase offset is also been tracked. In equalization state, the module will do data equalization and adaptive phase error tracking.

4.1.1.3 Architecture of CE error tracking

X 2µ

(phase)

-dl,k

el,k

sel 0

0

1

k

yˆl_,

Figure 4.5 – The architecture of the CE error tracking

Fig. 4.5 illustrated the architecture of the CE error tracking. It is simply implemented as a combinational circuit. Sel=0 When yˆ is in the trust area, and the _l,k output will be 2μe_l,k’, otherwise, the output will be 0 in order to stop CE adaptation.

4.1.1.4 Architecture of CE (magnitude)

+

RAM control output (preamble 1)

Data (preamble 2)

RAM countrol output (CFR)

1

Data (magnitude)

0

1

0

1 sel

sel

divider

>> 1

CFR

Output

(a) (b)

Figure 4.6 – CE module (a) Architecture, (b) finite state machine

The architecture of CE in magnitude is only 2 multiplexers and 1 divider (as the fig 4.6 shown). In state CE, sel is equal to 0, and the output CFR will be the estimated channel, again the estimated channel will be store in RAM control. In state

“equalization”, sel is equal to 1, the data will go through the divider and output the

equalized data.

4.1.2. Architecture of the CORDIC

With the original CORDIC algorithm, the range of the phase to be detected should between -π ~ π, which will be hard to express in 2’s complement. Also, the angular adder can not be implemented by conventional adder and should be redesign.

In the proposed design, the range of the angle is normalized with the 2/π, therefore, the range of the phase will be normalized from -2 to 2. The normalized phase is as shown in Fig. 4.7. It can be shown that the phases can be easily represented as 2’s complement form.

00.0(2)

00.1(2)

01.0(2)

01.1(2)

10.0(2)

11.1(2)

11.0(2)

10.1(2)

Figure 4.7 – The normalized phase

Besides, with the normalized phases, the adder does not have to be redesigned due to the proposed methodology. Even the overflow will happen, the result still accuracy. For example, the conventional calculation result of π/2 + 3π/4 = 5π/4 ( =

-3π/4), corresponsively, the proposed calculation result have same result of 01.0₍₂₎ + 01.1₍₂₎ = 10.1₍₂₎.

The other advantage is that, the proposed methodology can easily tell which quadrant does vectors belong to. It will reduce the complication of CE error tracking and phase error tracking.

In the de-CORDIC design, only 5-stage is needed because the resolution connecting with Viterbi decoder needs three bits.

4.2. Implementation issues

Hardware cost and system performance are trade-off in hardware implementation, so the fixed-point simulation will be needed before the implementation [8]. the following figure (Fig. 4.8) shows the fixed-point simulation result.

5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

float-point Resolution=18 Resolution=12 Resolution=10

SNR

Figure 4.8 – PER analysis with different word-length

According to the figure 4.8, when the resolution is lower than 12, the system performance will be decrease critically, so 12-bit resolution are chosen in the design.

In UWB system, clock rate 528 Mhz will be needed to meet the throughput rate 480Mbits/s, but it is too fast for logical design to approach it, so parallel circuit will be used to make the clock rate lower. The following table is the comparison between 2 parallel circuits and 4 parallel circuits.

Table 4.1 – the comparison between different parallel circuits

Clock rate Area Power

2 parallel circuits 264Mhz 51893

(54% CORDIC;

46% Equalizer)

N/A

4 parallel circuits 132Mhz 88390

(59% CORDIC;

41% Equalizer)

69.3826 mW

As the table shows, 2 parallel circuits only save about 30000 gate counts in hardware implementation. Although 2 parallel circuits design has lower area, 132 MHz is the major clock rate in our system integration. In order to reduce the complexity of system implementation, 4 parallel circuits design are chosen to be implemented.

4.3. Hardware synthesis

In this section, we discuss the implementation of the proposed equalizer design.

We use SYNOPSYS design compiler to synthesize the register-level verilog file with UMC 0.18μm slow library. The gate counters and the critical path delay of each module is shown in table 4.2, respectively.

Table 4.2 – Synthesis reports for each module

4.4. Soft IP Qualification

IP qualification is the key of SOC. As SOC become popular, the qualification of IP is more important. In this study, we also discuss about the IP qualification (IPQ).

IPQ defined the coding style. The verilog codes which follow the IPQ may be easier to understand. Table 4.3 shows the result of IP qualification.

Module Name Gate count Max. Path Delay (ns)

CORDIC (x4) 39450 5.57

De-CORDIC(x4) 12706 5.25

Ram_control 4648 5.18

Equalizer_phase 16456 5.66 Equalizer_length 16303 5.64

Table 4.3 – The result of IP qualification

Before Modification After Modification

Error 858 0

M1 & M2 1303 259

In our design, 251 warnings come from naming convention rule NC.7-1, which defined as use consistent signal names throghout the hierarchy. The rule can not be avoided if the circuit use repeatedly in a design. The fig. 4.9 shows the detail information of IPQ.

Figure 4.9 – The detail information of IPQ

In IP qualification, reasonable test patterns are needed for verification. The code coverage, which means the percentage of the verified design is checked in different verifying methodology, is used here to show how reasonable the test pattern is. In our

design, the code coverage of statement coverage, branch coverage and toggle coverage are almost 100%. The result is illustrated in fig. 4.10, and the table 4.4 list the met soft IP qualification.

Figure 4.10 – The code coverage of test patterns

Table 4.4 – The met soft IP qualification

Soft IP IP Designer Self-assessment Verification

[S.VG.1] verification plan M1 y

[S.VG.1.1] RTL dynamic simulation M1 y

[S.VG.1.2] All timing exceptions must be identified M2 y

[S.VG.2] Code coverage must be conducted and the coverage metrics must be documented and delivered.

M2 y

[S.VG.3] All response checking must be done automatically M2 y

The rules of writing testbench

[S.TB.1] testbenches must begin with a header M2 y

[S.TB.2] Testbenches must be written with comments R n

[S.TB.3] Keep line length within 72 characters in testbench codes R y

[S.TB.4] Testbenches should be partitioned into behavioral ans synthesizable sections

R n

IP prototyping

[S.PT.1] Soft IP prototyping M2 y

4.5. FPGA prototyping.

In FPGA prototyping, the input pattern is saved in Logic Analyzer (LA) and sent to FPGA. Then the result by waveform will sent back to the LA to dump the file for checking. In the proposed design, RAM will be used, but FPGA dose not support it, so in FPGA verification, Register file will be used to take replace RAM. The FPGA verification plan shows in Fig. 4.11, and Fig. 4.12 depicts the verifying situation.

Figure 4.11 – The FPGA verification plan

Figure 4.12 – Logic analyzer and FPGA board.

FPGA Logical Analyzer

Table 4.5 – Xilinx FPGA synthesis report.

Traget Device Xcv2000e-bg560

Slices 10449

Slices Flip Flops 9,905

Gate count 157,486

Timing 27.901ns ( 35.84 MHz)

4.6. Implementation results

The maximum clock rate is 164MHz, which throughput can approach 655MHz at maximum. The PAR process of layout is applied with SYNOPSYS ASTRO by UMC 0.18 μm. The chip feature shows in table 4.6, and fig. 4.13 depicts the macro layout view of equalizer.

Table 4.6 – Chip feature

Module name equalizer

Technique 0.18um CMOS, 1P6M

Gate count 88390

Macro Size 1470x1470

Clock rate 528MHz

Throughput 480Mbit/s

Power dissipation 69.3826 mW

Figure 4.13 – Macro layout view

Chapter 5.

Simulation result and performance analysis

5.1. Introduction

In this chapter we will discuss the design flow, system platform and performance for the proposed design. In this study, behavior model is built by Matlab, and then do system co-simulation with RF in Agilent ADS tool. The design flow is illustrated in Fig. 5.1. this kind of waterfall model can work well up to 100k gate count design.

After RTL code is development and verified, two ways are used for implement the design, one is ASIC, the other is FPGA prototyping. Both of them will be discussed in chapter 5. FPGA prototyping is for verifying hardware design in general, because FPGA can simulate the real world situations which we don’t concern before.

After that, we synthesis the design to gate-level netlist by reasonable design constrains, and check the timing, area and power, if all of them pass, we will run

Place & Route. After all, we check the timing, area and power again. If all of them conformed, the design is done.

Figure 5.1 – Design & verification flow

5.2. System platform

MUX MUX

Figure 5.2 – System platform for UWB system

Our system is illustrated in Fig. 5.2 [5]. The platform by MATLAB is based on 802.15.3a standard. The system platform it built for system performance analysis and function verification. Such as error vector magnitude (EVM), bit error rate (BER) and packet error rate (PER).

In system co-simulation, the baseband platform and the RF behavior model are combined together in Agilent ADS tool. It is because the information of RF simulation is viewed as timed sequence, so the sequences calculated by MATLAB should be packed and transformed into timed sequence, then RF team can check their parameter settings and performance, such as Tx EVM, Tx power spectrum, Rx sensitivity and PER etc. Fig. 5.3 shows the co-simulation platform.

Figure 5.3 – Co-simulation platform

5.3. Performance analysis

The proposed channel is simulated in the IEEE 802.15.3a system platform. The PER analysis will focus on the 8% PER, which is requirement in IEEE 802.15.3a.

5.3.1 CE error tracking Performance

To analyze the CE error tracking performance of the proposed channel equalizer, error vector magnitude (EVM) is measured. The EVM value of CE can be derived as equ. 5.1, where y_l,k is the data after equalization, x_l,k is the data from transmitter, which means ideal vector.



From the definition, if the EVM_dB is lower when system performance is better, the fig. 5.4 shows the EVM with and without CE error tracking in condition of CM2 channel model, 40ppm CFO, 40ppm SCO.

11 11.5 12 12.5 13 13.5 14 14.5 15 15.5 16

200Mbits/s, CM4, 40ppm CFO, 40ppm SCO

with CE error tracking without CE error tracking

Figure 5.4 – CE error tracking performance analysis

From the figure we can know, the proposed CE error tracking achieves 0.5~1dB gain in EVM compared with the system without CE error tracking.

To analysis the performance, packet error rate (PER) is also a target to achieve.

In IEEE 802.15.3a specification, PER is define as the probability of a 1024 byte packet miss, and should be less than 8%. The simulation of PER should be averaged

over a minimum of 50,000 realizations for each multi-path channel environment. The fig 5.5 shows the PER with and without CE error tracking. Notice that it achieves about 0.7 dB gain in PER compared with system without CE error tracking. The condition of the simulation is 200Mbits/s, CM4 channel and AWGN, 40ppm CFO and 40ppm SCO.

Figure 5.5 – CE error tracking performance analysis

5.3.2 Phase error tracking Performance

To verify the PET performance, the design is simulated under 40ppm CFO and 40ppm SCO, which is standard requirement. In the following simulation and

11 11.5 12 12.5 13 13.5 14 14.5 15 15.5 16

10⁰ 10¹ 10²

SNR [dB]

Packet Error Rate

200Mb/s, CM4, no CE error tracking 200Mb/s, CM4, with CE error tracking PER = 8%

comparison, the proposed design is compare to a simple PET algorithm, which realize

The algorithm only use 12 pilot subcarriers to against the phase offset, so the θ)_l and φˆ will be oscillate, just like the fig. 5.6 shows. The fig. 5.7 shows the EVM _l comparison between adaptive PET and without adaptive PET. PET with adaptive filter can against the noise. The fig. 5.7 is another PET performance analysis with EVM.

The figure shows that adaptive PET achieves 2.5 dB gains than other one. It increase the system performance a lot.

50 100 150 200 250 300 350 400 450 500 -0.4

-0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4

OFDM symbol #

phase offset tracking error

53.3Mbits/s, AWGN, 40ppm SCO, 40ppm CFO

with adaptive PET without adaptive PET

Figure 5.6 – The phase offset deviation analysis

11 11.5 12 12.5 13 13.5 14 14.5 15 15.5 16

-7.5 -7 -6.5 -6 -5.5 -5 -4.5 -4 -3.5 -3

SNR [dB]

EVM [dB]

200Mbits/s, CM4, CFO=40ppm, SCO=40ppm

with adaptive PET without adaptive PET

Figure 5.7 – PET performance analysis

5.3.3 System Performance

To verify the complete system performance of the proposed channel equalizer, PER of a complete IEEE802.15.3a basdband processor are measured with the Intel proposed indoor wireless channel model that contains 40ppm CFO and 40ppm SCO.

The PER curves of different transmission mode are shown in fig. 5.8.

The design SNR for 8% PER is listed in table 5.1. the table tells the proposed system has better performance in data rate of 480Mbits/s. The proposed baseband system achieves 1.05~6.09 dB gain in SNR compared with standard requirement.

Figure 5.8 – PER performance of the proposed baseband platform

2 4 6 8 10 12 14 16 18 20

10^-2 10^-1 10⁰ 10¹ 10²

SNR[dB]

Packet Error Rate

200Mb/s AWGN channel 480Mb/s AWGN channel 200Mb/s CM4+AWGN channel 480Mb/s CM2+AWGN channel PER = 8%

Table 5.1 – Required SNR for 8% PER of the proposed baseband platform

Data Rate

Design SNR (AWGN)

Design SNR (Multi-Path)

200Mbits/sec 4.11 dB 14.18 dB

480Mbits/sec 5.03 dB 15.01 dB

Data Rate

SNR Constraint (AWGN)

SNR Constraint (Multi-Path)

200Mbits/sec 5.16 dB 15.1 dB

480Mbits/sec 9.66 dB 21.1 dB

Chapter6.

Conclusions and Future Work.

6.1. Conclusions

Ultra Wide-Band uses OFDM system, which makes ultra wide-band system transmit in high data rates, but the system becomes sensitive to phase offset and phase noise. In this thesis, we propose a high speed and low complexity equalizer for WLAN IEEE 802.15.3a. In the proposed equalizer architecture, CORDIC module reduces the computation complexity of channel estimation, equalization, and phase error tracking.

IP qualification is the key of SOC, as SOC become more and more popular, IP qualification become more and more important. In this study, we consider the equalizer with soft IP qualification to achieve IP reuse.

6.2. Future Work

In the proposed equalizer architecture, CORDIC module reduces the computation complexity of channel estimation, equalization, and phase error tracking,

but it cost too much area. In the proposed design, CORDIC and de-CORDIC use about 50% of the total gate count of the equalizer. If there is more than one block need CORDIC module (like CORDIC based FFT [14]), then CORDIC can be share and reuse.

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簡 歷

姓名 : 張懷仁 性別 : 男 籍貫 : 雲林縣

生日 : 民國七十一年九月一號

地址 : 嘉義市西區福民里福州二街 46 號

學歷 : 國立交通大學電子工程研究所碩士班 93/09~95/06 國立暨南大學電機工程學系 89/09~93/06 協同私立高級中學 86/09~89/06

論文題目 : CORDIC based Equalizer for Ultra-Wide band system 用於 UWB 之 CORDIC based 等化器設計

在文檔中 用於UWB之CORDIC based 等化器設計 (頁 54-0)