Chapter 5 SC-FDE/OFDM Receiver for 60 GHz
5.6 Proposed Parallelized SCO Compensator
5.6.6 Implementation Results of SCO Compensation
Fig. 5-14 shows the block diagram of the hardware implementation. The blocks in the gray reign uses the synthesizable Veriolg hardware description language (HDL) and includes both the time interpolation method and the frequency rotation method.
The MUXs is used to change these two methods. The time interpolation method adopts the cubic B-Spline filter [71] which has better performance and lower complexity. The B-Spline filter uses the Farrow [47] structure which can decrease the usage of multipliers. In 8X parallelism, the time interpolation method totally requires sixteen interpolators for the real part and image part. The frequency rotation method uses 8 unrolling CORDICs. The FFT unit is a fixed pointed Verilog behavior model. To synchronize the latency of the FFT unit, a phase FIFO is added. The EQ is a floating point model and it is the same as that shown in Fig. 5-5.
The procedure of the simulation follows the Fig. 5-14. The transmitter shown in Fig.
5-5 generates the input samples and they are quantized into 10 bits. The quantized samples are fed into the Verilog model. Then, the output of the Verilog simulation is dumped and fed into the EQ to test the performance. Fig. 5-15 shows the performance results of the hardware implementation. In the time interpolation, the performance of the hardware is almost the same as that of the floating point. On the other hand, the performance of the hardware in the frequency rotation has about 1dB loss in high SNR reign but has almost no lose in design range( 9~30dB SNR).
Fig. 5-14 Block diagram the hardware implementation
Fig. 5-15 Performance Comparison
The synthesis results are shown in TABLE 5-6. The maximum operating frequency is 400 MHz in gate-level simulation and achieves 3.2GS/s. This throughput rate can meet the requirement of 802.15.3c, 2.64GS/s. The interpolators (B-spline filter) occupy the largest part in the time interpolation method; however, the time interpolation method has better performance in high SCO (500ppm) in OFDM mode.
In contrast, the frequency rotation method has lower complexity better performance in low SCO (50ppm). In short, for the SCO specification (50ppm) of 802.15.3c, the frequency rotation method has lower complexity and better performance at OFDM mode. However, considering the receiver of dual mode, the time interpolation is suitable for both the SC and the OFDM mode.
TABLE 5-6 Synthesis results
Process 90nm
Max. Operating Frequency 400MHz
Time Interpolation B-Spline filters 119K (58%)
Freq. Rotation CORDICs 38K (19%)
Shared
Elastic Buffers 15K (7%)
Others 32K (16%)
Total Gate Count 204K (100%)
5.7 Summary
In this chapter, an architecture of OFDM/SC dual mode baseband receiver is presented. This architecture includes a preamble/symbol detection, CFO/SCO synchronization loops, an OFDM/SC dual mode frequency domain equalizer.
Moreover, the behavior performance of OFDM mode is shown. When the received SNR is equal to 11dB, the BER can achieve 10-6. Besides, an overview of the time and frequency compensation method is presented. Then, a parallel architecture is proposed to speed up the SCO compensation. This parallel architecture can achieve
‘P’ times parallelism and there is no performance degradation due to the parallelism.
Finally, a design example of 8X parallelism is implemented. It operates at 400 MHz clock rate and achieves 3.2 GS/s .The gate counts of the time interpolation method are about 166K and that of the frequency rotation method are about 85K as shown in Fig.
5-16 .
Fig. 5-16 Pie chart of synthesis results
Chapter 6 Conclusion
In this thesis, an overview for effects of the frequency offset, channel models, and the link budget is first introduced. Several commonly used data-paths for a baseband receiver are also discussed. In addition, two baseband receivers are presented. One is OFDM receiver for DVB-T/H and the other one is an OFDM/SC dual mode receiver for 802.15.3c/802.11ad.
The proposed OFDM baseband receiver for DVB-T/H integrates a Mode/GI/Symbol detection, a multimode FFT, a channel estimation, a carrier frequency synchronization loop, a sampling clock synchronization loop. A ICFO/RCFO/SCO memory sharing architecture is proposed. In this architecture, ICFO estimation and RCFO/SCO estimation use the same memory block to reduce the hardware complexity. Besides, a differential encoding method for recoding the pilot location is adopted to reduce the capacity of the storage unit. The synchronization loops can compensate 50 sub-carrier spacing CFO and 200 ppm SCO.
The equivalent gate count of the proposed DVB-T/H receiver is about 810K gates including 102.8 KB memory. This receiver is fabricated in a 0.18µm CMOS technology and its core size is 12.96 mm2.
The architecture of the OFDM/SC dual mode baseband receiver for 802.15.3c/802.11ad includes a boundary detection, CFO/SCO synchronization loops, an OFDM/SC dual mode frequency domain equalizer. The boundary detection uses a
correlation-based method [70] and this method also estimates CFO. The baseband receiver assumes that the mixer and the ADC have the same reference clock. Hence, CFO and SCO use the same estimation. The OFDM/SC dual mode frequency domain equalizer uses LS-LMS method [68] to improve performance. When the received SNR is equal to 11dB, the coded BER performance of OFDM mode can achieve 10-6 in floating behavior simulation. Besides, a parallel architecture of the SCO compensation is proposed to speed up the operation. This architecture can achieve any
„P‟ times parallel and solve the irregular access from interpolators in parallel. In addition, a design example of 8X parallelism is implemented. It operates at 400 MHz clock rate and achieves 3.2 GS/s with about 204 K equivalent gate counts by using 90nm CMOS process and meets the data rate requirement of 802.15.3c/802.11ad.
Chapter 7 Future Work
The new application of DVB-T/H is to have higher mobility for usage during transportation. Hence, the Doppler Effect must be considered. The mobile environment makes the channel vary with time. The varying channel inferences the estimation of the frequency offset and channel estimation. Besides, more and more wireless broadband applications are operated in this environment. Therefore, estimating algorithms which can overcome the varying channel is an issue.
The SC mode of 802.15.3c/802.11ad inserts a period of known GI and the equalizer can use SC-FDE. However, SC-FDE requires two extra FFTs. By considering the characteristic of the 60GHz channel, the reflected paths have large path loss. Hence, the 60GHz channel has large probability to be a LOS channel which has one strong path and 2~3 small paths. A simple time domain equalizer (TEQ) which considers LOS channel may be adopted to reduce the hardware cost.
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作者簡歷
參與下列計畫
1.數位電視廣播接收器之數位解調與同步設計及其平台與晶片製作 2.室內無線十億級傳輸率之基頻傳收機與低功率設計技術
著作與論文
[1] Ting Chen Wei, W. C. Liu, C. Y. Tseng, and S. J. Jou, “Low Complexity Synchronization Design of an OFDM Receiver for DVB-T/H,” IEEE Trans.
Consumer Electronics, vol. 55, no. 2, pp.408–413, May 2009.[journal paper]
[2] Ting Chen Wei, W. C Liu and S. J. Jou, "A jointed mode detection and symbol detection scheme for DVB-T," IEEE Trans. Consumer Electronics, vol. 54, no. 2, pp.336–341, May 2008. [journal paper]
[3] Ting Chen Wei, W. C. Liu, C.Y. Tseng, S.S. Long, S.J. Jou, and M.T. Shiue “A 28mW OFDM Baseband Receiver Chip for DVB-T/H with All Digital Synchronization,” in Proc. IEEE CICC 2008, Sep. 2008, pp.351–354.
[conference paper]
[4] F. C. Yeh, T. Y. Liu, Ting-Chen Wei, W. C. Liu, and S. J. Jou, "A SC/OFDM Dual Mode Frequency-Domain Equalizer for 60GHz Multi-Gbps Wireless Transmission," in Proc. IEEE VLSI-DAT 2011, pp.406–409, Apr. 2011.
[conference paper]
[5] J. N. Lin, H. Y. Chen, Ting Chen Wei and S. J. Jou, “Symbol and Carrier Frequency Offset Synchronization for IEEE802.16e,” in Proc. IEEE ISCAS 2008, May 2008, pp. 3082–3085. [conference paper]
[6] W. C. Liu, Ting Chen Wei and S. J. Jou, “Blind Mode/GI detection and coarse symbol synchronization for DVB-T/H,” in Proc. ISCAS 2007, New Orleans, May 2007, pp. 2092–2095. [conference paper]
[7] C. Y. Tseng, Ting Chen Wei, W.C. Liu and S. J. Jou, “Low power and power aware design for DVB-T/H baseband inner receiver,” in Proc. IEEE VLSI-DAT 2007, Apr. 2007, pp. 1–4. [conference paper]
[8] W.C. Liu, Ting Chen Wei, and S. J. Jou, “Two-stage scattered pilot synchronization with channel estimation scattered pilots pre-filling for
DVB-T/H,” in Proc. IEEE VLSI-DAT 2007, Apr. 2007, pp. 1–4. [conference paper]