Improved aggregation of the NiSiGe nanocrystal by pre-capping oxide

5.3.1 Introduction

In this section, a NiSiGe film was deposited by co-sputtering approach. After the mixed film deposition, three kind of oxide thickness were deposited before the annealing process to improve the NC aggregation. After the RTA, it is found that the structure with a 20nm pre-capped oxide shows the most obvious NC aggregation among the samples by TEM analyses. EDS results were used to indicate the formed NC includes Ni, Si and Ge elements. Then, the effect of the pre-capped oxide for the NC aggregation during the forming process was proposed. In addition, the charge-storage ability of the formed NiSiGe NC memory devices has also been

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discussed by fabricating capacitor structure. Through the material and electrical results, we think the capped oxide method is easy and effective to improve the NiSiGe NC formation further.

5.3.2 Experiment

The fabrication of memory structure as shown as the Fig. 5-16 was started with a 5-nm-thick oxide grown on the p-type silicon wafer in APCVD furnace. Afterward a 6-nm-thick NiSiGe thin film was deposited by co-sputtering the NiSi2 and Ge targets, simultaneously. Then, 10- and 20-nm-thick capped oxide was deposited on the partial samples to form a tri-layer structure by PECVD. Subsequently, the samples were annealed in N₂ ambient at 600 ℃ for 30 sec, to form the NiSiGe NC structure. After the formation process, a total 50-nm-thick blocking oxide (SiO2) was formed by PECVD system. Finally, Al gate electrode was patterned to form the capacitance structure. After the fabricating of memory device, electrical measurements such as C-V, retention and endurance characteristics were used to study the charge-storage ability of the devices.

5.3.3 Result and discussion

Fig. 5-16 demonstrates the cross-section TEM images of the deposited NiSiGe film before and after the annealing process. The deposited NiSiGe film is about 6 nm as shown as the Fig. 5-16 (a). The forming process of NC is that atoms of the mixed

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film can diffuse if the thermal process provides enough energy. The diffused atoms were driven to form NC to reduce the internal energy of the self-assembled system [5.26]. Then, the interface stress and surface free energy induce the NC aggregate at the interface of tunneling oxide. However, it can be found that the NC cannot separate completely at 600℃ annealing process as shown as the Fig. 5-16 (b). A easy pre-capped oxide process before the NC formation can improve the separation of the NC as shown as Fig. 6-16 (c)-(d).

Fig. 5-17 is the EDS analyses of the formed NC structure to study the composition of the NC. During the EDS analyses, the electron beam was focused at the NC region about 10nm. Region a and b are the space and NC region, respectively. The main compositions of the NC include Ni, Si and Ge signal as shown as the EDS of region b.

In contrast, that region a only have slight Ni and Ge means the complete NC aggregation. Through the EDS analyses, it also confirms that the NiSiGe NC formation is through the aggregation of the elements during the thermal annealing.

The mechanism for the RTA system to accomplish the NC formation is through the heat provided by the light absorption of the Si substrate or the mixed film. The heat lose easily because the larger temperature gradient between the substrate and RTA chamber. Moreover, the pre-capped oxide play a heat-accumulation layer to reduces the heat loss behavior and enhances the NC aggregation even at lower temperature

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annealing process. Hence, the increase of the pre-capped oxide thickness brings a more complete NC aggregation.

To study the memory effect of the NC aggregation for the nonvolatile memory application, a high-frequency C-V characteristic was used as shown as the Fig. 5-18.

The sweeping gate voltage was set at ± 5V and ± 10V , which is defined by flat-band voltage of the devices. It is found that the incomplete aggregation degrades the electrical performance of the memory devices indeed. As the increase of the pre-capped oxide thickness, the C-V curve of the NiSiGe NC devices is improved obviously. The devices with 20 nm pre-capped oxide shows a 9V of △V_FB under the C-V measurement. In addition, related reliability measurements had been tested as shown in Fig. 5-19. The retention measurement was performed by operating a ± 10V gate voltage stress for 10sec and measured up to 10⁴sec. It is found that sample A maintains a 1.1V of △V_FB but sample B keeps a 2.2 V of △V_FB. The poorer retention maybe resulted from the leakage paths forms due to the incomplete segregation. The structure with 20 nm pre-capped oxide has superior charge-storage and retention characteristics to sample A due to the more complete NC aggregation.

Moreover, samples were tested by the continuous voltage pulse set at ± 5V for 1ms in the endurance measurement. A negligible degradation of the memory window is observed after a 10⁶ write/erase cycles operation in the samples because the endurance

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performance is related to the quality of the tunneling oxide, which was formed by the same APCVD process. It is confirmed that both the samples reveal a remarkable memory window, which is advantageous to provide an enough judgment for the logic circuit.

5.3.4 Conclusion

In conclusion, the aggregation of the NiSiGe mixed film has been discussed in this work. The more complete NC aggregation is found if the NiSiGe film was deposited a 20 nm pre-capped oxide before thermal annealing process. We think the pre-capped oxide provides a role of heat-accumulation layer to reduce the heat loss during the thermal annealing. Therefore, the NC aggregation can be achieved at lower fabricating temperature. In addition, it is confirmed that the NiSiGe NC formed with 20nm pre-capped oxide shows the best charge-storage performance by the measurements of the C-V characteristic, retention and endurance tests. The related material and electrical results exhibit that the NC formation with a pre-capped oxide is advantageous to lower the forming temperature.

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Fig. 5-1 Process of flow and device structure of this study.

Fig. 5-2 The plane-view and cross-section TEM micrographs of the annealed (a) NiSi and (b) NiSiGe film.

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Fig. 5-3 (a) The Ni 2p3/2 XPS spectra of the annealed NiSi and NiSiGe mixed film.

(b) The Ge 3d XPS spectra raw data and the fitting data of NiSiGe film after thermal annealing.

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Fig. 5-4 (a) Raman spectroscopy and (b) EDS of the NiSiGe film after thermal annealing.

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Fig. 5-5 The speculated picture for the formation process of the NiSiGe NC during RTA process.

Fig. 5-6 C–V characteristics (1 MHz) of the MOIOS structures: (a) with NiSi and (b) NiSiGe NC as the trapping layer of the memory device.

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Fig. 5-7 Retention characteristics of the (a) NiSi and (a) NiSiGe NC memory devices.

Fig. 5-8 Endurance characteristics of the (a) NiSi and (b) NiSiGe NC memory devices.

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Fig. 5-9 The cross-section TEM micrographs of the NiSiGe film after the (a) RTA and (b) RTO process for 60 sec.

Fig. 5-10 The C–V characteristics of the MOIOS structures: NiSiGe NC formed by (a) RTA and (b) RTO process.

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Fig. 5-11 The endurance characteristic of the NiSiGe film after (a) RTA and (b) RTO process.

Fig. 5-12 The retention characteristic of the NiSiGe film after (a) RTA and (b) RTO process.

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Binding Energy (e.V.)

28 29

30 31

32 33

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Int ens ity (a.u.) ^{Raw data}

Ge-O~32.5eV

(a) Ni-Si-Ge ~31.5eV

(b)

Ge-O~32.5eV

Ni-Si-Ge ~31.5eV

Ge-Ge~29.4eV

Fig. 5-13 The Ge 3d XPS spectra of the NiSiGe film after (a) RTA and (b) RTO process.

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Fig. 5-14 The J-V characteristics of the NiSiGe film after (a) RTA and (b) RTO process.

Fig. 5-15 The SIMS analysis of the NiSiGe NC formed by RTO process.

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Fig. 5-16 The cross-section TEM micrographs of the NiSiGe thin film.

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The capped oxide provides a role of heat-accumulation layer to reduce the heat loss during the thermal annealing. Therefore, the NCs aggregation can be achieved at lower fabricating temperature.

Cooling (b)

Fig. 5-17 The EDS analyses of the formed NC structure. Region a and b is the space and NC region, respectively.

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Fig. 5-18 The C-V results of the NiSiGe thin film (a) without, (b) with 10nm and (c) with 20 nm pre-capped oxide before the thermal annealing process, respectively. It is found that the structure with 20nm pre-capped oxide has the best performance among

the samples.

Fig. 5-19 Retention and endurance of the NiSiGe thin film (a&c) with 10nm and (b&d) with 20nm pre-capped oxide before the thermal annealing process.

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Chapter 6

Nitric acid oxidation for the tunneling oxide

application on CoSi

nanocrystal nonvolatile memory

6.1 Nitric acid oxidation of Si for the tunneling oxide application on CoSi

nanocrystal nonvolatile memory

6.1.1 Introduction

In recent years, the development of portable products market promotes the requirements of NVM devices. However, the tendency of device scaling down makes the conventional FG structure face the reliability challenges [6.1]. Therefore, distributed NC structure is thought as the solution of the issue because the charge is stored by individual trapping center [6.2]. In the research of NC memory devices, it can be found that the formation of tunneling oxide is still an important topic for the devices application because that the highest fabricating temperature of the current NC memory devices is not limited to the NC aggregation but the tunneling oxide deposition. A high-temperature furnace system is still the most common tool because the current NC memory devices need a tunneling oxide with adequate quality to assure its storage capacity [6.3-6.5]. Hence, a low-temperature oxide deposited technology is important for the advanced NVM devices [6.6-6.8]. Moreover, cost and throughput of the reported processes must be considered further to apply into the

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current devices fabrication. Recently, it is found that nitric acid oxidation is potential to form an enough quality oxide at lower temperature [6.9-6.10]. It is believed that more detailed discussions of the nitric acid oxidation method to form the dielectric layer are advantageous to the development of low-temperature memory device technology.

In this section, nitric acid solution (HNO3:H2O= 1:10) was used to oxidize the sputtered Si thin film. After the formation of nitric acid oxidized SiO2 (NAO-SiO2), metal-insulator-silicon (MIS) structure was fabricated to investigate the process of the nitric acid oxidation and the effect of the post-oxidation annealing (POA). It has been indicated the POA process plays an important role for the improvement of the NAO-SiO2 thin film by XPS analyses.Sequentially, a CoSi2 thin film was deposited on the NAO-SiO₂ layer to be the self-assembled trapping layer. After a thermal annealing process, it is found the CoSi₂ NC aggregated on the tunneling oxide obviously. The CoSi₂ NC memory device shows excellent memory window under the C-V measurement. Moreover, the related electrical characteristics of the memory devices such as the leakage current, charge-retention and endurance have also been demonstrated.

6.1.2 Experiment

Fig. 6-1 is the process flow of the experiment. The fabrication of memory

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structure was started with a sputtering process to form an about 2-nm-thick Si thin film on p-type (100) Si wafer which had been removed native oxide and particles by RCA process. Then, the Si film was immersed in the nitric acid solution (HNO3:H2O=

1:10) for 60 sec at room temperature to form the NAO-SiO2 layer. Portion of the NAO-SiO2 were fabricated to be the MIS structure. In addition, a 6-nm-thick CoSi2

film was deposited on the other portion of the samples by the sputtering system to be the self-assembled trapping layer. Then, the samples were annealed by RTA system set at 700℃ for 30sec in pure N₂ ambiance to form the CoSi₂ NC structure. After the RTA process, a 50-nm-thick blocking oxide was capped by plasma enhanced chemical vapor deposition system. Finial, top and bottom Al electrodes were patterned by a shadow mask to form MOIOS structure. After the fabrication of the devices, the related material and electrical analyses were used to analyze the CoSi₂ NC memory devices using the NAO-SiO₂ as the tunneling oxide.

6.1.3 Result and discussion

Fig. 6-2 (a) and (b) show the C-V and J-V characteristics of MIS structure using the NAO-SiO₂ as the gate oxide, respectively. In the Fig. 6-2 (a), the conditions of the samples are divided as (a) without and (b) with a followed 700℃ RTA treatment for 30 sec. The C-V measurement was swept from -3V to 3V to extract the quality of the oxide. It can be found that the sample without RTA treatment has an obvious (～0.5V)

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hysteresis. Moreover, the formed oxide without a POA process has an obvious leakage behavior at higher gate voltage operation and poorer uniformity of the electrical performance. However, it can be found that the hysteresis and leakage current can be improved by the followed 700℃ annealing process. From the results, we think that the improved characteristics may mean that an enough RTA process can reduce the defect of the NAO-SiO2 layer. We also extract the equivalent oxide thickness (EOT) through the C-V results. The EOT of the NAO-SiO2 with RTA at 700

℃ for 30 sec is about 4nm obtained by calculating the 88.56pF of the accumulation

capacitance in C-V curves. It can be found that the result fits in with the cross-section TEM image of the inset of Fig. 6-2 (a). In addition, the J-V characteristic of the MIS structure using the NAO-SiO₂ (after 700℃ annealing process) as the gate oxide has also been measured as shown as the Fig. 6-2 (b). The highest gate leakage current of the NAO-SiO₂ layer is about 10^-2A/cm² under -2V gate voltage operation, which is lower than the defined gate limit of the reported literature [6.11-6.12]. The result also indicates the NAO-SiO₂ without serious leakage current is potential for the application of the electric device. In the J-V result, a non-symmetric leakage behavior was found obviously. It can be explained that the higher gate injection current density under negative gate voltage is resulted from the electrons injected from the Al gate to the Si substrate. In contrast, a current saturation of the J-V characteristic is found when a

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positive gate bias is applied because the gate leakage current in the deep depletion region is related to the generation of minority carriers via the bulk traps and interface states in the depletion region [6.13].

Fig. 6-3 demonstrates the Si 2p XPS spectra of (a) the as-deposited Si film, the NAO-SiO₂ (b) before and (c) after the RTA at 700℃for 30sec process, respectively. It can be found that the Fig. 6-3 (a) shows a peak at about 99.3eV corresponding to the Si-Si bonding energy. In addition, we also found an additional peak at about 103eV, which is attributed with the native oxide formed during the sample fabrication. After the nitric acid immersion, an obvious Si elements transition to SiO2 means that most of as-deposited Si film was oxidized by the nitric acid solution as shown as the Fig.

6-3 (b). Also, some sub-oxide (SiOx, x<2) can be found that confirms the oxide still has a poorer quality. With an annealing temperature was used to improve the oxide quality, it is found that the Si-O peak was shifted toward higher binding energy and the sub-oxide element was reduced. The oxidation mechanism of the nitric acid oxidation is that the decomposition of HNO₃ can provide a high concentration of atomic oxygen with a strong oxidizing ability to oxidize the sputtered Si film. Hence, the oxidation can be accomplished by the brief nitric acid immersion and a POA treatment.

To study the feasibility for the NAO-SiO₂ layer to apply into the NC memory

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device, the MOIOS structure had been fabricated and measured. After the 700℃ RTA process, it is found the SiO2 formation and CoSi2 NC aggregation obviously as shown as the Fig. 6-4. The formed NAO-SiO2 film of the memory device is about 4nm and the CoSi₂ NC are about 6.5nm, respectively. The use of the 700℃ RTA is to promote the CoSi2 NC to be aggregated. According to the reported literature, an adequate external energy provided by the thermal system can induce the aggregation of the deposited CoSi2 thin film [6.14]. The total energy of the thin film is reduced when the surface area is minimized by forming a discrete and roughly spherical NC structure.

Moreover, XPS analyses were used to confirm the CoSi2 NC aggregation. The chemical composition of the charge-trapping layer is demonstrated in the Fig. 6-5 (a) and (b). It can be found that the main peak of 778.5eV in the Co 2p3/2 XPS spectrum corresponded to binding energy of CoSi₂ phase confirm the charge storage centers are mainly composed of CoSi₂ NC. The Co-Si signal also can be found in the Si 2p XPS of the trapping layer as shown as the Fig. 6-5 (b). Energy dispersive spectrometer (EDS) has also been used to analyze the compositions of the NAO-SiO₂ and NC as shown as Fig. 6-5 (c) and (d), respectively. In the Fig. 6-5 (c), the EDS of the NC region is composed of strong Co and Si signals attributed with the self-assembled CoSi₂ NC. In addition, only the Si and O elements can be found in the EDS results of the tunneling oxide reveals that the NAO-SiO₂ have enough quality to restrain the Co

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elements of charge trapping layer to diffuse into the Si-substrate even after 700℃

thermal annealing process as shown as Fig. 6-5 (d). We also used the secondary ion mass spectrometer (SIMS) to study the possibility of Co contamination further. Fig.

6-6 is the results of SIMS analysis for the CoSi2 NC memory device. It can be found that the main Co signal only accumulated at the tunneling oxide. Hence, it is believed that the Co contamination issue of the CoSi2 memory device using the NAO-SiO2 thin film as tunneling oxide can be been excluded.

Fig. 6-7 (a) shows the high-frequency (1MHz) C-V curves of the formed CoSi2

NC memory structure. While the gate voltage of the device was swept by ± 10V operation, a 7V of △V_FB can be observed. The counterclockwise of C-V hysteresis loops means the injected carrier is related to the inversion layer of the Si substrate.

The obvious memory window of the NC memory devices is advantageous to be the judgment of the logic circuit. In addition, the J-V characteristic of MOIOS structure was also investigated as shown as the Fig. 6-7 (b). Compared with the J-V result of MIS structure in the Fig. 6-2 (b), it can be found the MOIOS structure shows a lower leakage characteristic and symmetric behavior. The result is attributed with that the gate current of the MOIOS structure is determined by the blocking oxide, which restrains the passing electron in both the positive or negative gate voltage mode.

To study the reliability characteristics of the formed CoSi₂ NC memory device,

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retention and endurance characteristics have also been demonstrated. The retention characteristic of MOIOS structure was extracted by the capacitance-time (C-t) measurement as shown as the Fig. 6-8 (a). The normalized capacitance, △C_ret is defined as equation [1]:

△C_ret={ C(t)- C_FB}/ {C(0)-C_FB} [1]

, where C(0), C(t) and CFB of the equation [1] are the initial capacitance after the programming operation, the measured capacitance during the retention test and the referred capacitance at flat-band voltage, respectively [6.15]. The △C_ret of the memory device can be stable as about 48% of the initial capacitance after 10⁴sec test even if a obvious 20% capacitance drop within the first 100sec. In addition, we also demonstrated the endurance characteristic of the MOIOS structure as shown as Fig.

6-8 (b). The endurance characteristic of the device by the continuous voltage pulse set at ± 10V for 1msec. After the continuous stress, a followed C-V measurement was used to examine the degeneration of the memory charge-storage ability. A slight decay of the memory window is found even after 10⁶ cycles of pulse operations. The retention and endurance tests confirm the memory using the NAO-SiO₂ as tunneling oxide has an enough quality.

6.1.4 Conclusion

In conclusion, nitric acid oxidation method was studied to prepare a thin oxide as