CHAPTER 4 PROPOSED POWER EFFICIENT INTER-LAYER INTRA
4.6 S IMULATION R ESULT
To summarize the power efficient techniques discussed in Section 4.5, Figure 52 shows the composition of the power consumption when the intra prediction runs in SVC standard at
working frequency of 145 MHz. By applying second stage register sets in memory hierarchy and modified simpler interpolation decoding process, the SRAM and dynamic power are reduced due to memory access times and computational complexity. The second stage register sets not only reduce 62.3% of internal SRAM power consumption as compared to original only banked SRAM design, but also reduce the processing cycles by 45.51%. For dynamic power, modified Intra_BL decoding process can reduce 34% of power consumption due to the simpler operations. By these two methods, total power of SVC intra prediction engine can have 46.43% reduction.
Figure 52: Power reduction of proposed design.
The overall proposal description of SVC intra prediction engine is shown in Table 17.
Although the area overhead of power efficient proposal is about 22% compared to original design, the total power consumption and execution time can have significant improvements
with 46.43% and 45.51% reductions, respectively.
Chapter 5
Conclusion and Future Work
5.1 Conclusion
A power efficient SVC intra prediction engine is developed which supports high profile intra prediction in both H.264/AVC and SVC. This engine is consisted of two major prediction parts, which are basic prediction and Intra_BL prediction.
5.1.1 Basic Intra Prediction for H.264/AVC
We propose a high-profile intra predictor to support MBAFF and Luma intra_8x8 decoding. The proposed memory hierarchy includes upper, left and corner memory buffer which reuses the neighboring pixels for follow-up prediction procedures. In Luma_8x8 decoding process, we propose base-mode predictors to minimize the additional hardware cost, latency penalty, and filtered pixel buffer memory size. Compared to the existing design [16]
without supporting intra 8x8 coding, this design only introduce 10% and 7.5% of gate counts and SRAM overheads. The proposed design can achieve real-time processing requirement for HD1080 format video in 30fps under the working frequency of 100MHz.
5.1.2 Intra_BL prediction for SVC
We propose an Intra_BL prediction engine which supports different inter-layer prediction picture types. For the main interpolator design, the area efficient architecture is proposed by coef_generator, pixel_shifter, and scaling_engine. Coef_generator generates the each coefficient set of luma and chroma samples by some relationship between phase_idx and coefficient values. Pixel_shifter does some simple shifts for reference pixels, and
scaling_engine used to add the each combination from the pixel_shifter, and finally output the prediction pixels. Via these methods, the area cost can be reduced 26% at working frequency of 145MHz in UMC 90nm technology compared to the direct implementation.
To reduce the total power consumption in SVC intra prediction, second stage memory hierarchy and modified interpolation decoding process are further proposed based on our preliminary design. Second stage memory hierarchy transfers the significant power consumption in SRAM into four register sets. By adding these register sets, the power consumption in SRAM and processing cycles can be reduced by 62.3% and 45.51%.
Moreover, equality determination is used to simplify the computational complexity in basic interpolation. The modified Intra_BL decoding process can use simple shift instead of complex interpolation calculations. For dynamic power, 34% of power consumption can be reduced by this method. The total power consumption in SVC intra prediction engine can have 46.43% reduction by these two techniques. The proposed power efficient SVC intra prediction engine can achieve the maximum of two spatial layers with HD720 and HD1080 resolutions in 30fps under working frequency of 145 MHz.
5.2 Future Work
5.2.1 Error Concealment on Base Layer
Error correction is always a special and important issue in the video decoder. However, it is also hard to find a suitable method to implement due to the error propagation. A simple way to solve this problem is adding a big frame buffer to the design. However, this method is not appropriate to VLSI implementation, since that will cause a large area cost. Therefore, for the base layer decoding which uses the traditional H.264/AVC, the error issue is still a challenge.
5.2.2 Error Concealment on Enhancement Layer
On the other hand, the error correction in enhancement is easier to solve compared to base layer. Since the enhancement can use the information from base layer, this characteristic can also be applied to error correction. A method to solve the error block in enhancement layer is using the co-located block region in base layer. Different from upsampling process in SVC, we can use another simpler method called one-to-four to upsample the pixel instead of complex interpolation process. For the co-located pixels in base layer, we can directly extend the one pixel to be four pixels in enhancement layer (assume that the ratio of enhancement resolution to reference layer is 2:1). Figure 53 and Figure 54 show the results of upsampling method in one-to-four method and interpolation method. Although the reconstructed picture is not smooth as interpolation method, one-to-four is a simple method and a suitable way in VLSI implementation.
(a) (b)
Figure 53: (a) One-to-four method and (b) upsampling method in SVC for test sequence “glasgow”.
(a) (b)
Figure 54: (a) One-to-four method and (b) upsampling method in SVC for test sequence “suzie”.
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作 者 簡 歷
姓名：賴昱帆
戶籍地：台灣省台北市
出生日期：1984.09.24
學歷：2000.09 ~ 2003.06 國立建國高級中學
2003.09 ~ 2007.06 國立交通大學 電子工程學系
2007.09 ~ 2009.07 國立交通大學 電子工程研究所碩士班
得 獎 事 績
2009/05 2009 全國 IC 設計競賽設計完整獎
發 表 論 文
Yu-Fan Lai, Tsu-Ming Liu, Yao Li, Chen-Yi Lee, “Design of An Intra Predictor with Data Reuse for High-Profile H.264 Applications,” IEEE