Performance Analysis

For the decoder, Table 13 shows the average decoding cycles for one macroblock.

All the sequences in this simulation are in QCIF size and use all intra encoded to show the worst case situation. Due to the efficient decoding scheme, the proposed design can save up to 76% of cycles for Qp=28 case when compared to the previous one. For fair comparison, we implement the method proposed in and also include the required merging cycles in the previous design.

Table 13 Comparisons of Average decoding processing cycles

Qp Sequence Akiyo Foreman Stefan Mobile News

proposed 38 53 124 174 58

In this chapter, we describe the analysis and design of CAVLC decoder and UVLC decoder for H.264 video coding. The UVLC decoder takes the characteristic of exp-Golomb code to predetermine the code length. With the known code length, the hardware can be implemented in combinational logic instead of the tables in other VLC decoder designs. The proposed CAVLC design quickly skips redundant zero decoding cycles. For the CAVLC decoder, zero information is explored and works

together with partial multi-symbol decoding by employing the properties of the CAVLC algorithm. The CAVLC decoder design can reduce the decoding cycle by up to 76% for the QP=28 case when compared with others

Chapter 5

IMPLEMENT RESULT

5.1 memory controller

Table 14 List of gate count for memory controller

component gate count

write address generator 1366

read address generator 1797

write command generator 215

read command generator 215

arbiter and data masker 696

control unit 526

total 4832

The proposed data mapping aware memory controller is designed by Verilog HDL and implemented in TSMC 0.18um technology. When synthesizing at 133 MHz, the total gate count is about 4k. Table 14 lists the synthesis result of gate count for each component. The two address generators consume most of the total area. The available SDRAM operating rate under different CAS latency is as listed in Table 15.

When setting CAS latency to 3, the SDRAM can work at higher operating frequency.

However, more stall cycle is demanded due to the longer CAS latency. In our design, we set CAS latency to 2 and the maximum of available operating rate is 133 MHz. In this case, the frequency is fast enough to support the required bandwidth for real time decoding in our target formats.

Table 15 Maximum SDRAM operating rate under different CAS latency

Table 16 List of gate count for entropy decoder

Component Gate count

CAVLC decoder 11724

Coeff_token table 1764

Run_before table 737

Total_zero table 419

Level decoder 1312

Bit-stream shifter 1732

Datapath (merging unit, level buffer, coeff. buffer and zero detection unit)

5638

Control unit 105

UVLC decoder 1845

The proposed entropy decoder is designed by Verilog HDL and implemented in TSMC 0.18um technology. When synthesizing at 125 MHz, the gate count is about 11k for CAVLC decoder and 1.8k for UVLC decoder. Most of the CAVLC decoder area is spent on the datapath which includes the merging unit, level buffer, coefficient buffer and zero detection unit. Table 16 lists the detailed synthesis result of each component. The hardware cost comparison is listed in Table 17. For fair comparison, the hardware cost in [16] includes the level and run merging unit which is quiet the same as the proposed design. The design in [17] needs 6100 gates but without reordering and merging logic.

Designs [16] [17] Proposed Total gate count

(excluding memory)

9943 6100 11724

Process 0.18um 0.25um 0.18um

Frequency 125MHz 125MHz 125MHz

Table 17 List of hardware comparison of CAVLC decoder

Chapter 6

CONCLUSION

The contribution of this thesis can be divided in two parts. In chapter 3, a data mapping aware H.264/AVC memory controller is presented to improve the external memory bandwidth. To reduce the overhead cycles caused by the access characteristics of the SDRAMs, we analysis the statistics of video sequences and develop two methods to ease the memory access latency. For intra request optimization, we find a data mapping between image position and memory location to reduce the occurrence of row miss as possible as we can. For inter request optimization, we check the required row opening operation before access and skip the unnecessary row active and closing operation. As a result, the miss rate is about 1.8%

for 525SD video format with QP = 20 and the required bandwidth is 46.96MBps for real-time decoding of luma and chroma motion compensation.

In chapter 4, an entropy decoder with the capacity of partial multi-symbol decoding, zero skipping and skipped merging of run and level is proposed. The synthesis result shows that the gate count is about 11k for CAVLC decoder and 1.8k for UVLC decoder while the CAVLC decoder design can reduce the decoding cycle by up to 76% for the QP=28 case when compared with others designs. This design is very suitable for the applications with the demand of low power or high video quality

In the future work, the main idea of memory controller still works for advanced off-chip memories such as DDR or DDR2. The multi-channel technique and more complicated arbitration policy can work together with the proposed memory controller to enhance the performance for advanced coding tools like B-frame, weighted prediction and direct mode. The hardware cost of entropy decoder can be further reduced with optimized implementation of VLC tables. We sincerely hope that these research results can promote the improvement of video application and convenience of human life as well.

REFERENCES

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作 者 簡 歷

姓名： 余國亘 籍貫： 台灣桃園

學歷：

國立武陵高級中學 (民國 86 年 09 月~民國 89 年 06 月)

國立交通大學電子工程學系 (民國 86 年 09 月~民國 89 年 06 月)

國立交通大學電子所系統組 (民國 86 年 09 月~民國 89 年 06 月)

著作：

[1] G..-S. Yu, T.-S. Chang, “A zero-skipping multi-symbol CAVLC decoder for MPEG-4 AVC/H.264,” proc. ISCAS, pp. 4, May 2006