Gate Voltage (V)
4.2 Experimental Procedure
4.2.2 Investigation of Electrical Characteristics in Poly-Si TFT under Illumination Using Patterned Metal Shielding Layer
4.2.2 Investigation of Electrical Characteristics in Poly-Si TFT under Illumination Using Patterned Metal Shielding Layer
Figure 4.6 shows the ID-VG characteristics of shielding TFT with low drain bias measured in forward and reverse modes at dark. The exposure region is located close to the drain and source junction for forward and reverse measurement, respectively.
The two curves are almost identical and VTH of TFT in forward mode (Forward TFT)
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is as same as that of TFT in reverse mode (Reverse TFT). However, the VTH of Reverse TFT is slightly less than that of Forward TFT while drain voltage is 9V, as shown in Fig. 4.6. Since the shielding layer for Forward TFT has a gap in drain junction, the potential distribution coupling from drain voltage would not extend into channel region. Therefore, VTH of Forward TFT is independent of applied drain bias.
By contrast, the shielding metal of Reverse TFT is distributed over most of channel region from drain. It is indicates that the potential distribution induced by high drain voltage, VM, in the metal film of Reverse TFT would induce electrons in the back side to affect the VTH. In addition, the S.S of Forward TFT and Reverse TFT is unchanged by drain voltage at dark.
Figure 4.7 plots transfer curves of Forward TFT operated in linear region at the dark and photo states. As the gate bias is -12V, the leakage current of Forward TFTs is about 10-14~10-13 A at dark but is significantly increased under illumination. The IPLC is 2.5x10-11A, approximately three orders of magnitude greater than the dark leakage current. In addition, the S.S is slightly raised under illumination. The S.S under dark and photo states is 0.36 V/dec and 0.39 V/dec, respectively. As the drain bias is 9V, the ID-VG relationships of Forward TFT at dark and photo states are illustrated in Fig.
4.7. Similarly, a markedly high IPLC and the nearly unaltered S.S of Forward TFT under illumination are observed clearly. Since the width of depletion region at drain would be increased with high drain bias, the more electron-hole pairs induced by light would be separated in the depletion region. Therefore, in forward mode, the IPLC at high drain voltage is higher than that under low drain voltage.
The ID-VG characteristics of Reverse TFT are also investigated in this work, as shown in Figs. 4.8. As VD is 0.1V, the IPLC of Reverse TFT is 2.7x10-12A, as low as one order of magnitude, compared to that in Forward TFT under same drain voltage.
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Furthermore, the S.S of TFT under illumination in Fig. 4.8 is almost unchanged. The increase ratio of S.S in Reverse TFT is about 7.96% as drain bias is 0.1V. Figure 4.8 indicates that the S.S of Reverse TFT with high drain voltage, however, is substantially degraded under illumination. It is increased 64% of the magnitude of that at dark state. With high drain bias, the IPLC is also increased in Reverse TFT but still lower than that in Forward TFT. From the comparison in Forward TFT and Reverse TFT with high and low drain bias, it is inferred the significant increase of S.S in the Reverse TFT would be attributed to that the exposure region is located in source junction and the device is operated with high drain voltage.
For Forward TFT, the exposure region is located at the drain junction so that plenty of electron-hole pairs originated from light would be easily separated due to the electrical field at junction. Therefore, excess electrons could flow directly to the drain, leading to the IPLC, as shown in Fig. 4.9. By contrast, the exposure region of Reverse TFT is close to source side. As the drain bias is low, numerous electron-hole pairs generated in source junction is difficult to be separated by lateral electrical field.
Therefore, the excess electrons flowing to drain is fewer to cause the lower IPLC. However, as the drain voltage is high, a positive potential distribution, VM, in the metal film owing to the coupling effect is generated from the parasitic capacitance in the overlap of drain and metal shielding layer [4.11]. Hence, electrons induced by VM gather to form the back channel in the bottom of poly-Si layer, as illustrated in Fig.
4.9. So that excess electrons at source junction would flow to drain through the back channel and excess holes is residual to be accumulated in the source junction to form the floating body which offers a positive potential. It can be inferred that the degraded S.S in poly-Si TFTs under illumination is mainly caused by the floating body with positive potential near the source side. The key factors to affect IPLC and the S.S under
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illumination are clarified clearly using the patterned metal shielding layer in poly-Si TFTs.
When the gate bias is below the threshold and the semiconductor surface is in weak inversion or depletion, the corresponding drain current is the sub-threshold current. In weak inversion and depletion, the electron charge is small, the drain current is dominated the diffused electron from source in n-type poly-Si TFT. Therefore, it would be affected strongly by the barrier height of source. As the gate bias is applied, the barrier height of source is lowered to increase the amount of electron in channel diffused from source. Therefore, it is clearly observed that the S.S current is band diagram to explain the S.S degradation of poly-Si TFT is proposed, as shown in Fig. 4.10. First, as the excess electron-hole pairs are generated under illumination with positive drain voltage, the light-induced electrons flow to drain directly, forming the photo leakage current. Therefore, the residual excess holes are accumulated in the poly-Si film to form the floating body with a positive channel potential, ΔV. Hence, the source barrier is lowered by ΔV due to the floating positive potential distributed in the channel. While the applied gate bias is swept from negative to positive directions
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and smaller than the threshold voltage, TFT would be operated at sub-threshold region.
So the source barrier would be lower again by the positive gate bias. However, the more lowering source barrier induce that the excess holes accumulated in channel are more easily diffuse to the source to reduce the positive channel potential. So that the fewer channel potential leads to a raise of source barrier. It means that the source barrier is not only controlled by applied gate bias but also affected by the floating body with positive potential, ΔV when poly-Si TFTs are under illumination. In our method of treated TFT, the trap states on the top face of buffer layer can effectively recombine the excess electron-hole pairs induced by back light. So that amount of accumulated holes is also reduced effectively to suppress the effect of floating body.
Hence, the improvement of sub-threshold swing is clearly observed in this work. In addition, the results of shielding TFT confirm that the effective region affecting by floating positive potential is the source junction.
4.3 Conclusion
In conclusion, the IPLCand S.S properties of poly-Si are discussed in detail by two approaches. For treated TFT, the top surface of buffer layer is degraded by Ar ion bombardment. Due to the surface state densities induced by Ar ion implant, the excess electron-hole pairs are recombined directly. It is clearly found that the IPLC is significantly reduced, compared the conventional poly-Si TFT. Furthermore, the degradation of S.S in treated TFT under illumination is suppressed. In addition, this work explores the electrical characteristics of poly-Si TFTs under illumination using patterned metal shielding layer. The Forward TFT exhibits the significantly high IPLC
and the slightly modified S.S under illumination. By contrast, the IPLC in Reverse TFT is lower than that in Forward TFT at the same drain bias. The S.S under illumination is almost unchanged in reverse mode at low drain bias. However, a marked
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degradation in S.S is observed in Reverse TFT with high drain bias operation. The increased ratio of sub-threshold swing for this case is 64%. Based on the results and proposed model, the causes of IPLC and degraded S.S in poly-Si TFTs under illumination are demonstrated in this work.
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Fig. 4-1 The key process diagram for treating the surface of buffer layer using Ar ion implant bombardment. Numerous state densities are generated to be used as the recombination center for light-induced electron-hole pairs
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Fig.4-2 The proposed poly-Si TFT with patterned metal shielding layer. The width of exposure region is 3μm.
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Fig. 4-3 ID-VG curves of the conventional poly-Si TFT operated in the linear region under illumination and dark states. A significantly increase in leakage current and sub-threshold swing was observed.
-5 0 5 10 15
10-15 10-14 10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5
Dark Photo
Normalized Drain Current (A)
Gate Voltage (V)
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Fig. 4-4 The ID-VG characteristics in treated TFTs under dark state and photo state.
-5 0 5 10 15
10-15 10-14 10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5
Dark Photo
Normalized Drain Current (A)
Gate Voltage (V)
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Fig. 4-5 Explanation of current flow of poly-Si operated under illumination.
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Fig. 4-6 ID-VG characteristics of proposed TFT operated with low and high drain voltage in forward and reverse modes at dark
-5 0 5 10 15
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Fig. 4-7 ID-VG curves of poly-Si TFT in forward measurement as drain bias is 0.1V and 9V. A high photo leakage current and almost unchanged sub-threshold swing are observed.