Chapter 5 Hardware Architecture
5.3 Multistage K-Best Detection Architecture
5.3.1 Sorting Network
5.3.1.4 Linear-Sort
Area consumption in sorting network is associated with N because both the compare-and-select units as well as the registers grow proportionally to N. The results discussed above and shown in Figure 5-9 tell us that bubble-sort and bitonic-sort
require larger num s sort. Therefore, bubble-sort
and
dvantage of the circuit is the low silicon area. A drawback is that N cycles are needed to sort the N elements, i.e., linear sorting latency.
ber of comparators than M. Afghahi’
bitonic-sort are not really very good at all for our purpose.
In order to keep area small for larger K in multistage K-Best detector, we develop the circuit shown in Figure 5-10 and called linear-sort. The linear-sort is based upon small modifications to this design which is proposed by M. Afghahi [37].
It is consisted of N/2 compare-and-select units and requires N clock cycles to sort a sequence of N elements. Initially, all the registers are set to one. At each compare-and-select unit, the smaller value of the two inputs is passed to the lower output while the larger one is passed to the upper output. Therefore, after N clock cycles, the smallest K values will be stored at the bottom registers. The a
[Figure 5-10] Block diagram of linear-sorting network
5 n Unit
The architecture of the metric calculation unit at the first stage is shown in Figure 5-11. Figure 5-12 shows the architecture of the metric calculation unit at the ith stage ( 2 ≤ i ≤ q ) which executes the calculations corresponding to the equation (3.9) of the multistage K-Best algorithm. It consists of four n-bit adders, two n-bit × n-bit squarers and one carry save adder circuit, where n is the bit-width of the data path. From equation (3.10) and (3.11), we can see that the amount of calculations in the carry save adder circuit is different for different layers.
Resource sharing is applied. Therefore, the N candidates at the input of each stage are processed one after the other. As shown in Figure 5-11 and Figure 5-12, each candidate requires two clock cycles to update the accumulated partial Euclidean distance in the metric calculation unit. Then the updated accumulated partial Euclidean distance is delivered to the sorting network. The linear sorting network requires N clock cycles to sort a sequence of N candidates. Therefore, the total number of clock cycles for each stage is equal to N + 2.
.3.2 Metric Calculatio
[Figure 5-11] Architecture of metric calculation unit at the first stage
[Figure 5-12] Architecture of metric calculation unit at the ith stage (2≤ i ≤q)
5.4 Experiment Reports for Hardware Implementation
In this section, to evaluate the hardware implementation effectiveness of the proposed multistage K-Best detector, we have designed the hard-output multistage K-Best detector that can support 2 × 2 MIMO transmission with 64-QAM modulation.
Therefore, we report the experiment results in the following sub-section.
5.4.1 The Area and Power Estimation
The design entry is Verilog HDL language, which is synthesized to gate level implementation using Synopsys with 0.18um process technology. The whole
architec of the
QR-decomposition unit, matrix and vector multiplication unit and multistage K-Best detection unit are about 86K, 23K and 196K equivalent gates, respectively. Detailed reports can be found in Table 5-1.
The maximum clock frequency of the detector is 120MHz and the system can achieve up to 80Mbps throughput. For the power consumption issue, the power is estimated by PrimePower. The detector operates with a clock frequency of 120 MHz and the power for the detector is about 366mW. We use SOC Encounter as place and route (P&R) tool and the layout is shown in Figure 5-13. The core area of detector occupies about 2.080mm × 2.080mm = 4.3264mm2 and the die size is about 2.728mm
× 2.728mm = 7.442mm2.
ture consists of about 305K equivalent gates. The resource usages
[Table 5-1] Area report for each unit and component
[Figure 5-13] Chip layout by SOC Encounter
Chapter 6 Conclusion
6.1 Conclusion
This thesis has proposed a new signal detection algorithm which includes replacing the original higher order constellation with several lower order constellations and ordering the lower order constellation. Furthermore, application of the proposed algorithm significantly reduces the computational complexity compared to the conventional algorithm and achieves almost identical detecting accuracy.
Thus, the main contributions of this thesis are summarized as follows:
1. We compared the performance of the two tree search algorithms, multistage K-Best and conventional K-Best, for detection in the MIMO-OFDM system.
According to the simulation results summarized above, it can be seen that the two algorithms will produce almost the same PER performance at similar K values. However, the multistage K-Best algorithm is shown to achieve such performance with much lower computational complexity compared to the conventional K-Best algorithm.
2. The multistage K-Best architecture is presented. The architecture operates in a pipelined fashion and effectively supports 2 × 2 MIMO transmission with 64-QAM modulation. The hardware implementation is synthesized using 0.18um CMOS technology.
6.2 Comparison
In order to achieve high throughput with almost the same silicon area, we considered two designs: Design A contains one multistage K-Best detection unit with
ee identical conventional K-Best detection units with K = 8. We note that these designs can operate 2×2 antenna configuration and 64-QAM mod
K = 8; Design B contains thr
ulation scheme. Table 6-1 shows the implementation results of the two designs including the silicon area, detection throughput and power consumption. Due to the largely reduced number of required candidate, the detection throughput of Design A is almost 1.22 times larger than that of Design B with the similar clock frequency. At the same time the power consumption of Design A is smaller than Design B.
Reference Design A Design B
K 8 8
Antennas 2 × 2 2 × 2
Modulation 64-QAM 64-QAM
Gate Count 196 199.5
Throughput
@ 120 MHz [Mbps]
80 65.4
Power consumption
@ 120 MHz [mW]
180.9 239.1
[Table 6-1] Comparison of implementation results
6.3 Future Work
Performance may benefit from more sophisticated receiver such as iterative MIMO detection and decoding. This receiver consists of a MIMO detector and a channel decoder, as shown in Figure 6-1 [6]. The iterations are performed between the two units, such that the reliability of the decisions is increased. We know multistage K-Best algorithm can get benefits from decomposition higher order constellation for reducing overall complexity. Therefore, we can put the new idea into the iterative receiver, and then discuss the effects for computational complexity and performance by simulation results for the future work
] Block diagram of an iterative receiver [Figure 6-1
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