Chapter 5 Baseband Design and Chip Implementation
5.2 LOS MPIC Golay-MPIC TDE in Baseband Receiver
5.2.1 Chip Integration and Implementation Result
The block diagram excluding channel decoder of 8x parallel baseband receiver for IEEE 802.15.3c SC/HSI mode is redrawn in Fig. 5-11 where the dashed line represents control signals. The simulation models of overall baseband are built with MATLAB and Verilog HDL. The control of the data flow is in sequence block by block. In other words, the executed block will output control signals to trigger the next block and is then turned into sleeping mode to avoid redundant power consumption.
Fig. 5-11 Proposed block diagram of baseband receiver design
TSMC 65nm 1P9M general purpose process with voltage supply 1 V has update the library, and the new library becomes faster but larger power consumption as compared with the old library that the version I chip uses. We use the new library to implement this chip for TSMC tape-out flow, and synthesize this chip at 667 MHz by two kinds of library to compare the differences. Table 5-4 shows the new library has 1.42 times power consumption to the old library, but the areas are almost the same.
Table 5-4 Comparison of old and new TSMC 65nm GP process libraries
Old Library New Library
Area (Gate-count)
2416K 2407KPower (mW)
1169 1660The total area of baseband receiver circuit is about 2479K gate count. Fig. 5-12 illustrates the area proportion of each block circuit. The shared memory is shared by BD, TDE and PNC blocks. BD uses the memory in preamble period, and TDE uses it in data payload. Finally, PNC utilizes it in PCES field.
Fig. 5-12 Area proportion of each block circuit
Since the memory elements are replaced with register which is explained in Section 5.1.1, we can use TSMC 65 nm 1P9M general purpose (GP) process with voltage supply 1 V for higher clock rate and more timing margin for APR. The chip layout view is shown in Fig. 5-13. The core size is 2820μm × 2820μm with 88.93%
utilization density. The post-layout simulation shows that the proposed baseband
receiver design can achieve 336.7 MHz. Table 5-5 is the chip summary.
Fig. 5-13 2nd Chip layout view of the proposed baseband receiver Table 5-5 2nd Chip summary(using Golay-MPIC TDE)
Process
TSMC 65 nm 1P9M GP processSampling Frequency (MHz)
2640Clock Frequency (MHz)
330Total Gate Count
2915 KCore Area
7.95 mm2 (2.82 mm × 2.82 mm)Utilization
88.93 %Mode
SC HSIBER (uncoded) @ 12 dB
7.36×10-5 9.30×10-6Date Rate (Gbps)
3.52 5.28Power (mW)
1116.7Leakage Power (mW)
87.425.2.2 Measurement Consideration
As a result of 8x parallelism, the chip has massive input and output bits. However, we use different method from last version to verify this chip. For testing the function correction, we use high SNR data pattern, so the bit width of input data can be reduced to only 5 bits. In Fig. 5-14, the Pseudo Random Binary Sequence (PRBS) block will generate noise which is attached to the end of input data. In that way, we can save the area of stored pattern, and import data from outside.
Fig. 5-14 Testing diagram for measurement
Chapter 6 Conclusion and Future Work
6.1 Architecture Design Summary
This thesis proposes an adaptive LS-LMS FDE and LOS Goaly-MPIC TDE that can satisfy the dual mode (SC and HSI) specifications of IEEE 802.15.3c. The hardware of both methods can be shared by SC and HSI mode to reduce hardware complexity. The BER and sampling rate can achieve the requirement of IEEE 802.15.3c.
The LS-LMS FDE combines LMS adaptive algorithm with LS channel estimation.
The LMS algorithm has the advantage of low computational complexity and sufficient convergence speed with the aid of LS channel estimation. The simulation results show that the LS-LMS FDE can achieve 6.01*10-4 BER in SC mode and 9.68*10-3 BER in HSI mode (both uncoded) at SNR 12 dB. The total area is about 415K gate-count with 69% shared among SC and HSI mode except 2 FFT. The power consumption excluding FFT is only 81.27 mW when working at 400MHz.
On the other hand, the Golay-MPIC TDE uses MPIC equalization with Golay sequence-aided channel estimation. The MPIC algorithm can reduce the hardware complexity unlike traditional time-domain equalizer and Golay sequence-aided channel estimation will eliminate the AWGN noise. The Golay-MPIC TDE can achieve 2.53*10-4 BER in SC mode and 4.22*10-5 BER in HSI mode (both uncoded) at SNR 12dB. The total area is about 405K gate-count with 99% shared by SC and HSI mode. The power consumption is only 88mW when working at 400 MHz.
6.2 Chip Implementation Summary
The proposed different domain architectures are integrated in two indoor wireless communication baseband receiver systems. For the high speed and area efficiency considerations, the overall system designs are implemented using 65 nm 1P9M CMOS GP process under supply voltage 1.0 V.
The LS-LMS FDE chip occupies 7.81mm2 core area with 65.91% utilization, and the clock rate is 333 MHz. The data rate of SC and HSI mode can achieve 3.52 Gbps and 5.28 Gbps, respectively. Also, the power consumption is 793.98 mW. The shared memory is 32.68% of the baseband system which is shared by BD and FDE blocks.
The core area of Golay-MPIC TDE chip is 7.95 mm2 with 88.93% utilization, and the clock rate is 336.7 MHz. The data rate of SC and HSI mode can achieve 3.52 Gbps and 5.28 Gbps, respectively. Also, the power consumption is 1.12 W. The BD, TDE and PNC blocks use the same shared memory which is 37% of the baseband system.
6.3 Future Work
In the future, we will consider the modifications on the Golay-MPIC TDE algorithm to deal with the effects of variant channel and NLOS channel. As regards the chip implementation, we will reduce the core area and power consumption. Also, 10 Gbps data rate is our design target in the future. Higher QAM modulation, deeper pipeline, and more parallels architecture can achieve the 10 Gbps data rate goal.
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