Macroblock Level Rate Control Comparison

Five macroblock level rate control algorithms, which include SAD_MBL, ESAD_MBL, and TBRC, are used to test their characteristics and performances.

ESAD_MBL is used to solve the issue on SoC platform mentioned in previous section, TBRC is the approach which is suitable for hardware implementation, and SAD_MBL is used again to give comparison between frame level and macroblock level rate control. Another strategies, TM5 [7] and Rho-domain rate control described in section [18], are also taken into account.

5.3.1. PSNR

0 50 100 150 200 250 300

25 26 27 28 29 30 31 32 33

Macroblock Level PSNR Comparison Coastguard.cif 30fps 256kBps

Frame No

PSNR

First Order MB Level RD Model with SAD First Order MB Level RD Model with ESAD Table-Based Rate Control

Rho-Domain Rate Control Test Model 5

Fig 20. PSNR plots for COASTGUARD sequence

0 50 100 150 200 250 300

26 27 28 29 30 31 32 33 34 35

Macroblock Level PSNR Comparison Foreman.cif 30fps 256kBps

Frame No

PSNR

First Order MB Level RD Model with SAD First Order MB Level RD Model with ESAD Table-Based Rate Control

Rho-Domain Rate Control Test Model 5

Fig 21. PSNR plots for FOREMAN sequence

0 50 100 150 200 250 300 22

24 26 28 30 32 34 36

Macroblock Level PSNR Comparison Stefan.cif 30fps 768kBps

Frame No

PSNR

First Order MB Level RD Model with SAD First Order MB Level RD Model with ESAD Table-Based Rate Control

Rho-Domain Rate Control Test Model 5

Fig 22. PSNR plots for STEFAN sequence

Generally speaking, the two rate control methods, ESAD_MBL and TM5, are not very well. TM5 is designed for MPEG-2 video coding which is adequate for high bitrate encoding and there is no syntax limitation in adaptation of quantization parameter, so this might introduce degradation in quality. ESAD_MBL, which is used to remedy the interrupt service time, bases on the modeling units in previous frame to obtain QP for current frame. The main issue is that the actual information like QP, SAD, and number of coding bits could not be acquired, so the previous frame is used to estimate QP and results in low quality.

The three mechanisms, SAD_MBL, Table-based rate control, and Rho-domain rate control, has similar quality. Rho-domain RC applies impressive mapping between QP and percentage of quantization DCT coefficients and has good performance. SAD_MBL, which uses delicate conception, is close to result of Rho-domain RC. Although TBRC has little degradation on PSNR, it still has result close to Rho-domain RC. In addition, TBRC is adequate for hardware implementation and could be designed with efficient circuit.

5.3.2. Frame Bits Variation

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0 1 2 3 4 5 6

7x 10⁴ Macroblock Level Bits Variation Comparison Coastguard.cif 30fps 256kBps

Frame No

Bits

First Order MB Level RD Model with SAD First Order MB Level RD Model with ESAD Table-Based Rate Control

Rho-Domain Rate Control Test Model 5

Fig 23. Frame bits plots for COASTGUARD sequence

0 50 100 150 200 250 300 0

0.5 1 1.5 2 2.5 3 3.5 4

4.5x 10⁴ Macroblock Level Bits Variation Comparison Foreman.cif 30fps 256kBps

Frame No

Bits

First Order MB Level RD Model with SAD First Order MB Level RD Model with ESAD Table-Based Rate Control

Rho-Domain Rate Control Test Model 5

Fig 24. Frame bits plots for FOREMAN sequence

0 50 100 150 200 250 300

0 2 4 6 8 10

12x 10⁴ Macroblock Level Bits Variation Comparison Stefan.cif 30fps 768kBps

Frame No

Bits

First Order MB Level RD Model with SAD First Order MB Level RD Model with ESAD Table-Based Rate Control

Rho-Domain Rate Control Test Model 5

Fig 25. Frame bits plots for STEFAN sequence

In the point of view in frame bits variation, ESAD_MBL has apparent amplitude, which implies the capability of QP prediction is not good and could not control number of frame bits very well. The variation of SAD_MBL, TBRC, Rho-domain RC, and TM5 are the frame bits similar to the some fixed value, and this implies they could control the output bitrate very well to match the target rate.

5.3.3. Buffer Status

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0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

Macroblock Level Buffer Fullness Comparison Coastguard.cif 30fps 256kBps

Frame No

Buffer Usage

First Order MB Level RD Model with SAD First Order MB Level RD Model with ESAD Table-Based Rate Control

Rho-Domain Rate Control Test Model 5

Fig 26. Buffer status plots for COASTGUARD sequence

0 50 100 150 200 250 300 0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

Macroblock Level Buffer Fullness Comparison Foreman.cif 30fps 256kBps

Frame No

Buffer Usage

First Order MB Level RD Model with SAD First Order MB Level RD Model with ESAD Table-Based Rate Control

Rho-Domain Rate Control Test Model 5

Fig 27. Buffer status plots for FOREMAN sequence

0 50 100 150 200 250 300

-0.2 0 0.2 0.4 0.6 0.8 1 1.2

Macroblock Level Buffer Fullness Comparison Stefan.cif 30fps 768kBps

Frame No

Buffer Usage

First Order MB Level RD Model with SAD First Order MB Level RD Model with ESAD Table-Based Rate Control

Rho-Domain Rate Control Test Model 5

Fig 28. Buffer status plots for STEFAN sequence

In Fig 26, there is large gap between TM5 and other approaches. This results from the large error of first I-frame and the different design for calculating target frame bit. Other methods use similar updating policies for frame bits, so the difference is small. Such as the plots in frame bits variation, ESAD_MBL has large amplitude compared to other approaches, and SAD_MBL has the most stable variation which is close to some fixed value in FORMAN and COASTGUARD sequences and almost one straight line in STEFAN sequence. Because SAD_MBL distributes the as equivalent number of bits as possible among all macroblocks, it can attain the target number of frame bits more correctly.