Chapter 2 A CMOS 2.45 & 5.25 GHz Self-Biased Dual-Band
2.3 Circuit Design
2.3.4 Matching Networks
(a) (b)
Figure 2.9 (a)Self-biasing Vt reference with start-up circuit (b)Schematic of PMOS capacitor
Figure 2.10 shows the simulated transient plot of the biasing circuit to simulate the turn-on situation of the real supply voltage. It indicates that the bias circuit can respond immediately even when Vcc turns on in just 10 sµ .
Figure 2.10 Transient plot of biasing circuit
2.3.4 Matching Networks
Instead of using the maximum power transfer theorem (gain match condition), it usually adopts power match condition for RF power amplifiers since the power transistors have larger device peripheral compared with those used in different functions [34]. It’s not entirely clear how to define impedances in a large-signal,
Strat-up CKT
nonlinear system. A more important reason is that even if we can solve the problem and subsequently arrange for a complex conjugate match, the current swing of the PA’s would be limited by the device I-V curve, resulting in 1-3dB lower output power compared with power matched PA’s, and the efficiency would be only 50% because equal amounts of power are then dissipated in the source and load. Consequently, PA’s usually have small optimum load resistance to achieve as large as output power, PAE, etc..
The so-called load- / source- pull measurements are the most practical and precise way to measure the large signal characteristics. One of the commercial computer controlled load-pull measurement system is shown in Figure 2.11. The purpose to measure the output is to derive the maximum output power, and that to measure the input is to derive the minimum reflected power.
Figure 2.11 Focus computer controlled load / source pull measurement system
Figure 2.12 is the load-pull simulation environment of ADS, it helps to predict the output power of each load impedance on Smith chart. And from the load- / source- pull measurement results, designers can clearly know how to match the transistor by those constant power contours.
(a)
(b)
Figure 2.12 (a)ADS load-pull simulation environment (b)Simulation results
A major hindrance for full integration onto a single chip using standard CMOS technologies is that the on-chip passives, such as inductors, capacitors, and filters, require high-Q values, which is also one of the challenges of designing the dual-band matching networks. The conventional matching topologies include low pass-high pass diplexer, switched element filter network, and a combination of both [32]. For the sake of high Q values and verification of the topology, the input / output matching networks presented in this design, as shown in Figure 2.13, is in diplexer form utilizing Murata lumped-elements and microstrip transmission lines. Theoretically,
the 2.4- and 5.2-GHz input signals are fed from the single port through a low-pass filter (LPF) and high-pass filter (HPF), respectively. After the signals are amplified with a common amplifier, they are divided again by an LPF and HPF and delivered to output port. In the diplexer-matching configuration, signal isolation between frequency bands must be maintained.
The off-chip matching networks also have its convenience for some tuning if there is any mismatch between simulation and practical situation. By tuning these elements, the desired impedances of each interested band can be synthesized.
Figure 2.13 Diplexer –liked dual-band matching network
2.4 Layout Considerations
The driver amplifier is laid out using LAKER layout tool. The die, as shown in Figure 2.14, which occupies an area of 0.85 mm by 0.7 mm, was mounted chip-on-board on Rogers RO4003 PCB. Four bond-pads are used to ground the source of the transistor for preventing from source degeneration and unstable condition, which result in an inductance of about 0.75nH. Additional pad is added between biasing circuit and the driver amplifier to measure the bias circuit’s output and to supply bias voltage directly if the bias circuit does not operate properly. Furthermore, for metal density and antenna rule concern, diode-liked cells are added to the free space of the die. To cope with the process variation, the resistor R2 of the biasing
circuit in Figure 2.9 is laid out with a width of 5 mµ (normally 2 mµ ), and the dummy resistors are also equipped.
(a)
(b)
Figure 2.14 The (a)layout and (b)die photo of the dual-band pre-amplifier
The input DC-blocking capacitor is implemented with 12.8pF MIM capacitor 0.7mm
0.85mm
formed by 25 MIM capacitors of 515fF for the concern of Q and the output one is also implemented as large as 14.4pF. Each of the elements is surrounded by guard ring fabricated using bottom Metal connected to Si-substrate and can also be bonded-wire to PCB to provide a more clean environment for the integration with other front-end circuits, such as, LNA, Mixer, VCO.
2.5 Simulation and Measurement Results
The circuit is simulated using both Agilent ADS and Mentor Eldo-RF. The bond-wire effect, off-chip matching networks, biasing circuit, and the variation of process, temperature, and supply voltage are considered in the simulations.
z Measurement Considerations
Figure 2.15 shows the board level photo of the CMOS driver amplifier. In the beginning, though the foundry of the monolithic elements provides model files (*.s2p) of their products, it’s found that some of the elements do not perform quite well at high frequency (above 5-GHz), especially for larger capacitance and inductance. This leads to serious mismatches between simulation and measurement, and becomes the main challenge to design the matching circuits at 5.25-GHz.
Figure 2.15 Board level photo of the dual-band driver amplifier
To solve the problem, each element is measured to re-build the model files for simulation. Figure 2.16 indicates the ”Through, Reflection, Line (TRL)” calibration way. It’s worthy to note that the frequency of λ4 line of “Load” is 4.0-GHz since we wonder the frequency band of 2.0-GHz to 6.0-GHz. It’s an effective solution to re-design the matching network.
Figure 2.16 TRL calibration
As a matter of course, on PCB measurement is adopted. The measurement can be done by the setups shown in Figure 2.17 to measure such as, S-parameters, P , Gain, 1dB PAE, and IP3, etc.. Figure 2.18 shows the practical measurement setups provided by the Chip Implementation Center (CIC), P , Gain, and IP3 can be measured by these 1dB instruments. And S-parameters are measured by Agilent 8720ES S-parameter Network Analyzer.
During the measurement, some amplifiers still start to oscillate or be broken even that they are stable and work properly in the initial stage. There are several points for attention: (1)50Ω loads should be connected to the input and output to terminate the reflection when measuring the DC characteristic. This protection is useful to avoid DC oscillation. (2)Ground should be connected first when using the power supply. If the positive electrode is connected first, the supply voltage will not be predictable (even above 20-V), and the circuit will suddenly be broken. (3)Because it needs quite high temperature to weld the SMA connector, the latter should be welded after the former becomes cooling. (4)Be careful when using the buzzer of the multimeter to
check if there is any short-circuit because the meter will provide a DC voltage about 1.2-V, which may cause damage to the amplifier. (5)Another issue of using power supply is that the voltage should be tuned slowly. If the tuned voltage variation is too large, it may become a trigger to lead to circuit oscillation. (6)Static ring is proposed to be put on all the time for preventing from the ESD issue. (7)Decouple capacitors should be placed at both Vbias and Vcc to eliminate the feedback path.
(a) (b)
(c)
Figure 2.17 Various setups used to measure the performances of the PA:
(a)S-parameters (b)P , Gain, PAE (c)IM3, IP3 1dB
Figure 2.18 Measurement setups
z Performances at 2.45-GHz
Figure 2.19 and Figure 2.20 show the power parameters. The P1dB occurs at Pin
= 2.0dBm and the corresponding Pout = 8.3dBm with PAE = 17.1%. Figure 2.21 indicates the two-tone test (with f1=2450-MHz and f2=2451-MHz) with IIP3 = 13dBm and OIP3 = 16dBm.
Pin (dBm)
-20 -15 -10 -5 0 5 10
Pout (dBm) & Gain (dB)
-15 -10 -5 0 5 10 15
Pout (Sim.) Gain (Sim.) Pout (Meas.) Gain (Meas.)
Figure 2.19 Pout & Gain vs. Pin @ 2.45-GHz
Pin (dBm)
-20 -15 -10 -5 0 5 10
Pout (dBm) & Gain (dB)
0 10 20 30 40
PAE (Sim.) PAE (Meas.)
Figure 2.20 PAE vs. Pin @ 2.45-GHz
Figure 2.21 Two-tone test IIP3 and OIP3 measurement result @ 2.45-GHz
z Performances at 5.25-GHz
Figure 2.22 and Figure 2.23 show the power parameters. The P1dB occurs at Pin
= 4.0dBm and the corresponding Pout = 7.2dBm with PAE = 9.3%. Figure 2.24 indicates the two-tone test (with f1=5250-MHz and f2=5251-MHz) with IIP3 = 15dBm and OIP3 = 19dBm.
Pin (dBm)
-20 -15 -10 -5 0 5 10
Pout (dBm) & Gain (dB)
-20
Figure 2.22 Pout & Gain vs. Pin @ 5.25-GHz
Pin (dBm)
Figure 2.24 Two-tone test IIP3 and OIP3 measurement result @ 5.25-GHz
The S-parameters shown in Figure 2.25 indicate this driver amplifier can work both in 2.4-GHz frequency band and 5.2-GHz frequency band with reasonable performances.
The self-biased dual-band CMOS driver amplifier is fabricated by TSMC 1P6M 0.18 mµ process. Matching networks are needed to be fabricated on PCB. Table 2.2 is the performance summaries and comparisons of the CMOS driver amplifier. From Table 2.2 we can observe that the gain performances are poor than the simulation results and cause the PAE decreasing with that, especially for 5.2-GHz band. Since the P1dB and gain of PA are sensitive to the input and output matching networks, it’s reasonable to suspect that the amplifier is not really matched well.
The S-parameters in Figure 2.25 indicate that the matching condition is not as bad as imagine, however, the S-parameters are derived with an input power of -25dBm. In other words, there may be something wrong with the matching condition if input power becomes larger.
Frequency (GHz) Figure 2.25 S-parameters (a)S11 (b)S21 (c)S12 (d)S22
Table 2.26 and Table 2.3 show the S-parameters with an input power of 5dBm, it can be observed that the 2.4-GHz band still has good matching networks, but the input return loss (S11) of 5.2-GHz is only about -6dB, which is the reason for poor performances of 5.2-GHz band.
In conclusion, we must consider the large input power operation of PA when designed, especially for high frequency. It is essentially not clear how to define the large signal model and impedance, which is the minor reason makes the PA design difficult. Table 2.4 is the comparisons between this works and recently papers.
Table 2.2 Performance summaries
Dual-band Driver-amplifier (TSMC 0.18 mµ CMOS)
Supply Voltage (V) 1.8
Figure 2.26 Return loss @ Pin = 5dBm (a)input return loss (b)output return loss Table 2.3 Return loss @ Pin = 5dBm
Table 2.4 Comparisons of the dual-band driver amplifier with the previously
CMOS 2400 <17.5 <13.9 <16 Meas.
[10]
Chapter 3
A 2.4GHz Si/SiGe BiCMOS Class F Power Amplifier for Bluetooth Application
3.1 Specification Introduction ― Bluetooth
The Bluetooth standard defines short-range wireless connection between mobile phones, mobile PCs and other portable devices. It specifies a 2.4-GHz frequency-hopped spread-spectrum (FHSS) system that enables the users to easily connect to a range (10m-100m) of computing and telecommunication devices without the need for wires or cabling of any kind. Space and cost considerations are among the primary motivators for the drive toward a single-chip radio solution.
Bluetooth communication occurs in the unlicensed Industrial Scientific Medicine (ISM) band from 2400 to 2483.5 MHz. The transceiver utilizes frequency hopping to reduce interference and fading. This means that every 625μsec. the channel will hop to another frequency. The communication channel can support both data (asynchronous) and voice (synchronous) communications with a total bandwidth of 1 Mb/sec.. The supported channel configurations are shown in Table 3.1.
Table 3.1 Supported channel configuration in Bluetooth system
Configuration Max. Data Rate
Upstream
Max. Data Rate Downstream 3 Simultaneous Voice Channels 64 kb/sec. 3 channels× 64 kb/sec. 3 channels×
Symmetric Data 433.9 kb/sec. 433.9 kb/sec.
Asymmetric Data 723.2 kb/sec. or 57.6 kb/sec. (upstream) 57.6 kb/sec. or 723.2 kb/sec. (downstream)
The modulation scheme is Gaussian Frequency Shift Keying (GFSK), with frequency deviations of 160KHz around the carrier. A binary system is used where a
“1” is signified by a positive frequency deviation and a “0” is signified by a negative frequency deviation. Based on signal transmission distance, the required transmitter power levels are classified to Class 1, Class 2, and Class 3, which are shown in Table 3.2. All Bluetooth classes are rated at about 1Mb/sec., with next generation products allowing anywhere from 2 to 12 Mb/sec..
Table 3.2 Three power class of Bluetooth system
Power Class Maximum Output Power
1 100mW (20dBm)
2 2.5mW (4dBm)
3 1mW (0dBm)
Most portable Bluetooth devices will probably be in Power Class 2 or 3 (with a nominal output power of 4dBm or 0dBm) due to cost and battery life issues. A Power Class 1 device requires the utilization of a power control to limit the transmitted power over 0dBm. While a little more costly and power hungry, this will provide up to 100m of range, which should be sufficient for home networking and other applications that require a greater range.
3.2 General Consideration
3.2.1 Process Choice
Recently, there has been increasing applications of SiGe based BiCMOS to RF analog ICs in the cellular phones and in the wireless local area network systems, commercially. The current RF CMOS circuit and device design technology provides a useful solution for other RF circuits, but on the other hand, CMOS PA is far away
from clear design methodology. SiGe has the advantages of its high frequency characteristics over Si and higher potential of functional integration over GaAs.
Moreover, process stability based on large size wafer Si LSI process technologies results in high yield, and offers lower chip costs. SiGe heterojunction bipolar transistors (HBTs) have also attracted much attention for RF power application because of their good microwave power performance, which becomes almost compatible with those of HBTs made of compound materials [35-38]. For the RF power transistors used in the power amplifiers of cellular phones, generally over 1W output power drivability is needed.
z Comparison of the key design parameters of Si-BJTs and SiGe-HBTs From a designer’s point of view, SiGe-HBTs are very similar to Si-BJTs. Basic principles gained in Si-BJT circuits can therefore be applied to SiGe-HBT circuit design in a straightforward manner. There are certainly several advantages of the SiGe technology:
(a) For a given collector current density, SiGe-HBTs require an input voltage VBE that is lower as compared to pure silicon bipolar technology. This holds particularly, when the “true” heterojunction bipolar concept – in comparison with the drift transistor concept favored by other companies – is used: Due to the heterojunction effect, the collector current density is increased exponentially with the difference in bandgap between emitter and base, which is in turn proportional to the germanium (Ge) content in the base. Although part of this gain is sacrificed to a base doping concentration that is 10-20 times higher as compared to Si-BJT technology, to achieve a given collector current density, an input voltage VBE is sufficient that is about 80-mV lower as compared to the Si-BJT. This is especially useful when moving to lower supply voltages, as demanded by all mobile communication systems.
(b) The SiGe heterojunction bipolar concept with inversion of the doping levels in emitter and base used in the process makes use of a lightly doped emitter layer.
This reduces base-emitter capacitance CBE drastically and therefore high speed and high gain can be achieved at a lower current density which is profitable to low power design.
(c) The high current gain achievable improves the input resistance and the low noise properties in the input stages of LNAs.
(d) Due to the high base doping concentration, the base width modulation by the base-collector voltage is less pronounced, leading to a higher early voltage as compared to Si-BJTs. This allows for high output resistance of amplifier stages and the realization of very stable current sources.
(e) Because of the high gain at frequencies above 2-GHz, a linearization by feedback is possible, which provides a good inter-modulation behavior in power amplifiers and low noise amplifiers.
The major disadvantage of Silicon bipolar technology for communication systems is the low breakdown voltage, which makes the high power design a demanding task. PA devices must withstand high voltage excursions (quantified by voltage standing wave ratio, VSWR), together with large current densities to survive in the hostile environments expected for consumer articles such as wireless telephones.
The low breakdown voltage BVCEO is hereby not a problem specific to SiGe but is a problem of all advanced Silicon bipolar processes, where the transit time is determined not any more by the base width but by the width of the collector layer.
z SiGe BiCMOS for power amplifiers
Power amplifiers are a core component in the high growth wireless communications industry. PA’s are rapidly evolving in both architecture and the communication protocols which they must address. Bipolar transistors are the critical
building block of a PA, with silicon, slicon-germanium (SiGe) and Ⅲ/Ⅴ technologies competing as the technology of choice. The constant current gain as a function of temperature together with the high current density and low thermal resistance of the PA SiGe HBT technology makes it possible to make use of smaller output devices thereby minimizing parasitic effects. The low parasitics increase the inherent gain of the devices, which together with an efficient biasing scheme can be utilized for achieving high efficiency.
The technology used in this work is TSMC 0.35 mµ 3P3M Si/SiGe BiCMOS process. Based on a volume-process presented in [39], [40], it features a bipolar junction transistor (BJT) with a f over 40-GHz and a three layer Al-metalization T with a 2.8 mµ thick upper layer.
3.2.2 Nonlinear Amplifier
As 2.2.3 introduces, another approach of PA is to use the device as a switch, the reasoning being that a switch ideally dissipates no power, for there is either zero voltage across it or zero current through it. Since the switch’s I-V product is therefore always zero, the transistor dissipates no power and the theoretical efficiency must be 100%. The trade-off is poor linearity due to the switching nature. Therefore, switched-mode power amplifiers can only be suitable for the systems with constant envelope modulation scheme.
z Class D PA
The typical circuit of Class D PA is shown in Figure 3.1. Driving signals are applied to the gates in opposite polarities. The FETs are biased at the verge of conduction and the drive causes them to switch on and off alternately.
Figure 3.1 Schematic of Class D PA
During the half cycle when M1 is on, Vdrain1 = 0, hence a voltage –VCC is coupled to the output-transformer network. During the half cycle when M2 is on, a voltage of +VCC is similarly coupled to the output-transformer network. Since the voltage at the dc feed-point is fixed at VCC, the drain voltage waveforms are square waves with levels of 2VCC and 0.
The fundamental frequency component of the square wave on the output of T2
passes through the output filter to become the output voltage. The sinusoidal current following in the series-tuned output filter requires a corresponding current to flow through one drain or the other. The drain current waveforms are therefore half sinusoids. The current flowing into the dc feed-point of T1 is the sum of i and D1 i , and is therefore a full wave rectified sinusoid. Ideally, the drain voltage is zero D2
when the drain current is flowing, and the drain current is zero when the drain voltage is not. Consequently, an ideal Class D amplifier is 100% efficient.
One practical problem with this PA is that there is no such thing as a perfect switch. Nonzero saturation voltage guarantees static dissipation in the switches while finite switching speeds imply that the switch I-V product is nonzero during the transitions. Hence, switch-mode PA’s function well only at frequencies substantially below f . Furthermore a particularly serous reduction in efficiency can result in T bipolar implementations if, due to charge storage in saturation, one transistor fails to