3.3 Comprehensive gate driver circuit
3.3.4 Measurement results
Fig. 3.29 shows the architecture of proposed GOA(III) and this architecture is fabricated on glass in Fig. 3.30. The circuit is also measured by Keithly 4200-scs and oscilloscope. Then, Fig. 3.31 and shows the outputs of GOA(III) and those are not only correctly but also low fluctuation. By the measurement result in Table 3.11, the speed of output1 is slower than other outputs because first stage without Vt compensation. Therefore, the stage with Vt compensation can reduce 36.36% rise time and 18.75 fall time.
3.3.5 Summary
The conventional noise-free circuit has the problem of static power consumption and lifetime. Then, the input of prior GOA can’t pass full range of supply voltage due to the Vt drop. This propose GOA provide the concept of eliminating static power consumption and the methods of expanding life time and speed up. By these manner, the GOA is more suitable for high resolution panel
Ca
corresponding control signals and output.Stage1 In
Out(1)
Stage2
Out(2)
Stage3
Out(3)
Stage4
Out(4)
Stage5 clk
xclk
Out(5)
Fig. 3.2 Architecture of the first proposed circuit GOA (I)
Fig. 3.3 The simulation result of node A(n) with different decoupling capacitance
Table 3.1 The simulation data of node A1
Voltage of A(1)
Ca At T3
period
Maximum by clock feed through
0.1pF 34.6 V 1.74 V
0.3pF 32.9 V 0.898 V
0.5pF 31.3 V 0.267 V
Table 3.2 The simulation information of output1 Speed of Out(1)
Ca rise time
(sec)
fall time (sec)
0.1pF 2.66E-05 1.68E-05
0.3pF 3.07E-05 1.82E-05
0.5pF 3.52E-05 1.98E-05
Fig. 3.5 The fabricated on-panel circuit for GOA and the corresponding measurement setup.
CLK
M1 M2
M3 M4
Cb Out(n)
600/4
30/4 100/4
30/4
Out(n+1)
2pF
Out(n-1)
Fig. 3.6 Schematic of the GOA (Thomson’s scheme) cell
(a)
(b)
Fig. 3.7(a) The layout of fabricated GOA (I), (b) The die photo of fabricated GOA (Thomson’s scheme)
Fig. 3.8 Measurement result of (a)GOA (I) (b) GOA (Thomson’s scheme)
Table 3.3 (a) Measurement data of GOA(I)
Measurement Rise time (µs) Fall time (µs) RMS of fluctuations (V)
OUT(1) 24 20 0.468
OUT(2) 48 28 0.272
OUT(3) 52 28 0.340
OUT(4) 46 24 0.448
Table 3.3 (b) Measurement data of GOA (Thomson’s scheme) Measurement Rise time (µs) Fall time (µs) RMS of
fluctuations (V)
OUT(1) 54 36 0.559
OUT(2) 50 32 0.451
OUT(3) 48 28 0.472
OUT(4) 60 28 0.559
ROW
Fig. 3.9The four type of polarity inversion.
1st gate line
2nd gate line
3rd gate line
N-1th gate line
Nth gate line
Pre-charge pulse
Write in pulse
[ For Dot & Row inversion]
[ For Frame & Column inversion]
1st gate line
2nd gate line
3rd gate line
N-1th gate line
Nth gate line
Fig. 3.10 The two kinds of two pulse scanning waveforms for corresponding polarity inversion.
Out(n-1) CLK
Out(n-1)
Fig. 3.12. (a) The timing diagram of proposed circuit and (b) Waveform variation of A(n) and B(n).
IN_2 XCLK CLK
Out(1) Out(2) Out(3)
A(1)
Vdd+
B(1)
T1 T2 T3 T4 T5 T6 T4'
pre-charge
Fig. 3.13 The timing chart and output waveform for dot inversion mode.
Fig. 3.14 The timing chart and output waveform for frame inversion mode.
stage1
Row & dot inversion mode Column& frame inversion mode
Input stage (output of timing controller)
Normal mode Row & dot inversion mode Column& frame inversion mode
Output type GOA system
Fig. 3.16 The block diagram of the proposed gate driver with tri-operated modes
Normal, row, and dot inversion
mode CLK XCLK XCLK CLK
Column and frame inversion
Fig. 3.17 (a)
Fig. 3.17 (b)
Fig. 3.17 (c)
Fig. 3.17 The simulation waveforms of GOA(II) from 1st, 2nd, 3th and 4th stage with (a) Normal mode, (b) Dot & row inversion mode, and (c) Frame & column inversion mode
Table 3.5 the simulation results of GOA(II) with (a) Normal mode, (b) Dot inversion mode, and (c) Frame inversion mode
Simulation
(a)
(b)
Fig. 3.18 The simulation waveforms of (a)A(n) and Out(n) (b)A(n) and
Out(n-1) CLK
Fig. 3.19 The schematic diagram of the GOA(II) with increasing aspects.
Table 3.6 the simulation results of GOA(II) with increasing size and
Fig. 3.20 The layout of fabricated GOA (II)
(a)
(b)
(c)
Fig. 3.21 The output waveforms of GOA(II) from 1st, 2ed, 3th and 4th stage with (a) Normal mode, (b) Dot inversion mode, and (c) Frame inversion mode
(a)
(b)
(c)
Fig. 3.22 The output waveforms of GOA(II) from 10th, 20th, 30th and 40th stage with (a) Normal mode, (b) Dot & row inversion mode, and (c) Frame & column inversion mode
Table 3.7 the measurement of GOA (II) with Normal mode.
Measurement Rise time (µs) Fall time (µs) RMS of fluctuations (V)
OUT(1) 30 25 0.22
OUT(2) 40 35 0.124
OUT(3) 35 25 0.097
OUT(4) 30 20 0.584
OUT(10) 24 14 0.1424
OUT(20) 26 16 0.073
OUT(30) 26 16 0.0469
OUT(40) 26 18 0.0792
OUT(100) 25 20 0.0345
Table 3.8 the measurement of GOA (II) with increasing size and voltage range.
Measurement Rise time (µs) Fall time (µs) RMS of fluctuations (V)
OUT(10) 6 8 0.085
OUT(20) 5 7 0.055
OUT(30) 6 6 0.0363
OUT(40) 5 8 0.086
OUT(100) 5 7 0.0214
ML
MD
IN
OUT Vx
Fig. 3.23 The controlling circuit of noise-free circuit in the conventional GOA .
M8 M1
Fig. 3.24 Schematic of (a) the third proposed circuit GOA (III) cell and (b) the corresponding control signals and outputs.
Fig. 3.25 The simulation waveforms of GOA(III) from 1st, 2nd, 3th and 4th stage.
Table 3.9 The simulation results of GOA(III).
Simulation
(Normal mode) Rise time (µs) Fall time (µs) RMS of fluctuations (V)
OUT(1) 7.65 4.39 0.016588
OUT(2) 7.05 3.9 0.017518
Fig. 3.26 The simulation waveforms of GOA(III) and the comparison with design of Vth drop compensation.
M8 M1
Fig. 3.27 Schematic of GOV(III)_v which is the GOA(III) replaces C1 by Mc .
Fig. 3.28 The simulation waveforms of B(n) and the comparison between GOA(III) and GOA(III)_v.
Table 3.10 Comparison with GOA(III) and GOA(III)_V Simulation RMS of fluctuations (V)
GOA(III)
RMS of fluctuations (V) GOA(III)_V
Average of Out (1~4) 0.041672 0.049301
Fig. 3.29 The architecture of proposed GOA(III) cell.
Fig. 3.30 Layout of proposed GOA(III) cell.
Table3.11 Comparison with Vt compensation
Simulation Rise time (µs) Fall time (µs) RMS of fluctuations (V)
OUT(1) 22 16 0.0131
OUT(2) 14 13 0.0082
OUT(3) 17 15 0.0207
OUT(4) 14 13 0.0481
Fig. 3.31 Measurement of Proposed GOA(III).
Chapter 4
Conclusions
4.1. Conclusions
We fit the practical spice model of a-Si TFT for circuit design and simulate. Then, we successfully verify the proposed gate driver circuits using a-Si TFT on glass substrate.
In the first part, the proposed circuit reduce 35.71% layout area due to the method of adjusting clock’s duty and concept on charge sharing.
Moreover, this GOA provides the stable signals by decoupling capacitor.
The second proposed GOA(II) system without logic gate which can provide three kinds of scan signals. These pre-charge signals are suitable for high resolution panel. Furthermore, the design of noise-free circuit not only ensure stable output but also reduce the size of output pull-down TFT.
The final proposed GOA uses the inverter with capacitor load to replace the pseudo NMOS inverter and eliminates static power consumption. Furthermore, the pull-down transistors suffer the lower stress and the lifetime can be extended by two alternately paths of noise-free. Then, GOA(III) has the bigger driving ability by
compensation of Vth drop. This design can reduce 7.8% charging time and 11.1% discharging time.
4.2. Future work
In the future, we will devote to practical implant the a-Si gate driver circuits on application of panel. Then, the panel with a-Si gate driver will test in the various conditions of temperature and long time voltage stress.
Finally, we will research the reliability issue by these experiment.
References
1. S. M. Sze, “Physics of Semiconductor Devices”, Wiley, New York (1981).
2. M. Quirk and J. Serda, “Semiconductor Manufacturing Technology,”
Prentice-Hall, Inc., Upper Saddle River, New Jersy 07458. (2001) 3. Donald A. Neamen, “Fundamentals of Semiconductor Physics and
Devices,” McGraw-Hill, New Youk (1992)
4. 戴亞翔, “TFT-LCD 面板的驅動與設計 (Design and Operation of TFT-LCD Panels ),” 五南圖書出版股份有限公司, Taiwan (2006) 5. C-W Lin, T-K Chang, C-K Jan, M-H Hsieh, C-Y Tsai, S-C Chang,
and Y-M Tsai “LTPS circuit integration for system-on-glass LCDs,”
Journal of the SID, 14/4, 2006, pp. 353 – 365.
6. Y-H Tai, C-C Pai, B-T Chen, and H-C cheng “A Source-Follower Type Analog Buffer Using Poly-Si TFTs With Large Design Windows,” IEEE Electron Device Lett.,vol.26,No.11, pp. 811-813, Nov. 2005.
7. W-J Nam, J-H Lee, H-J Lee, H-S Shin, and M-K Han “Peripheral circuit designs using low-temperature p-type poly-Si thin-film transistors,” Journal of the SID, 14/4, 2006, pp. 403 – 409.
8. Thomson Consumer Electronics, S.A., France, “Phase Clocked Shift Register with Cross Connecting between Stages,” United States Patent 5434899(1995)
9. J.- H. Oh, J.-H. Hur, Y. D. Son, K.-M. Kim, S.-H. Kim, E.-H. Kim, J.-W. Choi, S. –M. Hong, J.-O. Kim, B.-S. Bae, and J. Jang, “2.0 inch a-Si:H TFT-LCD with low noise integrated gate driver,” SID Dig. Tech., 2005, pp. 942 – 945.
10. RCA Thomson Licensing Corporation, Princeton, N.J. “Shift Register Useful as a Select Line Scanner for a Liquid Crystal Display,” United States Patent 5410583(1995)
11. S. Edo, M. Wakagi, and S. Komura, “A 2.2” QVGA a-Si TFT LCD with High Reliability Integrated Gate Driver,” SID Dig. Tech., 2006, pp. 1551 – 1552
12. Samsung Electronics Co., Ltd. “Shift Register and Display Device Having The Same,” United States Patent 7319452(2008)
13. LG Display Co., Ltd. “Shift Register,” United States Patent 7477226(2009)
14. LG Display Co., Ltd. “Shift Register and Driving Method Thereof,”
United States Patent 7532701(2009)
15. Chunghwa Picture Tubes, Ltd., Taoyuan “Shift Register and Shift Register Apparatus Thereof” United States Patent 7590214(2009) 16. Samsung Electronics Co., Ltd. “Gate Driving Circuit and Display
Apparatus Having The Same,” United States Patent 7369111(2008) 17. S.-F. Chen, L.-H. Chang, J.-R. Chen, S.-C. Lin, C.-M.Yu, J.-H. Hsu,
18. Y.R. Fan, W.J. Dai, M. Lv, Peter Liao, Smart Chung, CT Lee and TS Jen, “A Repairing Method for the Interlaced Gate Driver In Array (GIA) Circuit,” IDW, 2009, pp. 1733 – 1736.
19. Samsung Electronics Co., Ltd. “Liquid Crystal Display Apparatus,”
United States Patent 7522145(2009)
20. Mitsubishi Electric Corporation, “Shift Register Circuit and Image Display Apparatus Equipped with The Same,” United States Patent 7636412(2009)
21. S.-H. Lo , C.-C. Wei, W.-C. Lin, IF Wang , C.-C. Shih, and Y.-E. Wu,
“Integrated gate driver circuit with one conduction path for charge-discharge,” SID Dig. Tech., 2006, pp. 231 – 234.
22. A. S. Sedra and K. C. Smith, “Microelectronic Circuits,” Oxford University Press, Inc., New York. (2004)
23. C-L Lin, C-D Tu, M-C Chuang, K-W Chou, and C-C Hung. “A Highly Stable a-Si:H TFT Gate Driver Circuit with Reducing Clock Duty Ratio”- SID Dig. Tech., 2010, pp. 1360 – 1362
24. S-J Pak, J-H Lee, H-G Kim, and M-W Lee, “Shift Register Display Device Having The Same and Method of Driving The Same,” United States Patent Application Publication 2006/0001637 A1(2006)
25. S. Uchikoga, “Low-temperature polycrystalline silicon thin-film transistor technologies for system-on-glass displays,” in MRS Bulletin, pp. 881−886, Nov. 2002.
26. B. Lee, Y. Hirayama. Y. Kubota, S. Imai, A. Imaya, M. Katayama, K.
Kato, A. Ishikawa, T. Ikeda, Y. Kurokawa, T. Ozaki, K. Mutaguch, and S. Yamazaki, “A CPU on a glass substrate using CG-silicon TFTs,” Tech. Dig. of IEEE International Solid-State Circuit (ISSCC), 2003, vol. 9, No. 4, Feb. 2003.
學經歷
姓名：林俊傑 性別：男
生日：民國七十四年十一月四日
地址：108 台北市萬華區昆明街 274 號 4 樓 學歷：台北市立大同高中 (90.9~93.6)
國立海洋大學電機工程學系學士 (93.9~97.6)
國立交通大學顯示科技所碩士班 (97.9~99.6)
碩士班論文題目：非晶矽薄膜電晶體液晶顯示器閘極驅動電路之研究