34 Chapter 9 Memory Management
9.4 When a process is rolled out of memory, it loses its ability to use theCPU(at least for a while). Describe another situation where a process loses its ability to use the CPU, but where the process does not get rolled out.
Answer: When an interrupt occurs.
9.5 Given memory partitions of 100K, 500K, 200K, 300K, and 600K (in order), how would each of the First-fit, Best-fit, and Worst-fit algorithms place processes of 212K, 417K, 112K, and 426K (in order)? Which algorithm makes the most efficient use of memory?
Answer:
a. First-fit:
b. 212K is put in 500K partition c. 417K is put in 600K partition
d. 112K is put in 288K partition (new partition 288K = 500K - 212K) e. 426K must wait
f. Best-fit:
g. 212K is put in 300K partition h. 417K is put in 500K partition i. 112K is put in 200K partition j. 426K is put in 600K partition k. Worst-fit:
l. 212K is put in 600K partition m. 417K is put in 500K partition n. 112K is put in 388K partition o. 426K must wait
In this example, Best-fit turns out to be the best.
9.6 Consider a system where a program can be separated into two parts: code and data. The CPUknows whether it wants an instruction (instruction fetch) or data (data fetch or store).
Therefore, two base–limit register pairs are provided: one for instructions and one for data.
The instruction base–limit register pair is automatically read-only, so programs can be shared among different users. Discuss the advantages and disadvantages of this scheme.
Answer: The major advantage of this scheme is that it is an effective mechanism for code and data sharing. For example, only one copy of an editor or a compiler needs to be kept in memory, and this code can be shared by all processes needing access to the editor or com-piler code. Another advantage is protection of code against erroneous modification. The only disadvantage is that the code and data must be separated, which is usually adhered to in a compiler-generated code.
9.7 Why are page sizes always powers of 2?
Answer: Recall that paging is implemented by breaking up an address into a page and offset number. It is most efficient to break the address into X page bits and Y offset bits, rather than perform arithmetic on the address to calculate the page number and offset.
Because each bit position represents a power of 2, splitting an address between bits results in a page size that is a power of 2.
Answers to Exercises 35
9.8 Consider a logical address space of eight pages of 1024 words each, mapped onto a physi-cal memory of 32 frames.
a. How many bits are there in the logical address?
b. How many bits are there in the physical address?
Answer:
a. Logical address: 13 bits b. Physical address: 15 bits
9.9 On a system with paging, a process cannot access memory that it does not own; why? How could the operating system allow access to other memory? Why should it or should it not?
Answer: An address on a paging system is a logical page number and an offset. The physical page is found by searching a table based on the logical page number to produce a physical page number. Because the operating system controls the contents of this table, it can limit a process to accessing only those physical pages allocated to the process. There is no way for a process to refer to a page it does not own because the page will not be in the page table. To allow such access, an operating system simply needs to allow entries for non-process memory to be added to the process’s page table. This is useful when two or more processes need to exchange data —they just read and write to the same physi-cal addresses (which may be at varying logiphysi-cal addresses). This makes for very efficient interprocess communication.
9.10 Consider a paging system with the page table stored in memory.
a. If a memory reference takes 200 nanoseconds, how long does a paged memory refer-ence take?
b. If we add associative registers, and 75 percent of all page-table references are found in the associative registers, what is the effective memory reference time? (Assume that finding a page-table entry in the associative registers takes zero time, if the entry is there.)
Answer:
a. 400 nanoseconds; 200 nanoseconds to access the page table and 200 nanoseconds to access the word in memory.
b. Effective access time = 0.75(200 nanoseconds) + 0.25(400 nanoseconds) = 250 nanoseconds.
9.11 What is the effect of allowing two entries in a page table to point to the same page frame in memory? Explain how this effect could be used to decrease the amount of time needed to copy a large amount of memory from one place to another. What effect would updating some byte on the one page have on the other page?
Answer: By allowing two entries in a page table to point to the same page frame in memory, users can share code and data. If the code is reentrant, much memory space can be saved through the shared use of large programs such as text editors, compilers,and database systems. “Copying” large amounts of memory could be effected by having dif-ferent page tables point to the same memory location.
However, sharing of nonreentrant code or data means that any user having access to the code can modify it and these modifications would be reflected in the other user’s “copy.”
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9.12 Why are segmentation and paging sometimes combined into one scheme?
Answer: Segmentation and paging are often combined in order to improve upon each other. Segmented paging is helpful when the page table becomes very large. A large contiguous section of the page table that is unused can be collapsed into a single segment table entry with a page-table address of zero. Paged segmentation handles the case of having very long segments that require a lot of time for allocation. By paging the segments, we reduce wasted memory due to external fragmentation as well as simplify the allocation.
9.13 Describe a mechanism by which one segment could belong to the address space of two different processes.
Answer: Since segment tables are a collection of base–limit registers, segments can be shared when entries in the segment table of two different jobs point to the same physi-cal location. The two segment tables must have identiphysi-cal base pointers, and the shared segment number must be the same in the two processes.
9.14 Explain why it is easier to share a reentrant module using segmentation than it is to do so when pure paging is used.
Answer: Since segmentation is based on a logical division of memory rather than a phys-ical one, segments of any size can be shared with only one entry in the segment tables of each user. With paging there must be a common entry in the page tables for each page that is shared.
9.15 Sharing segments among processes without requiring the same segment number is possi-ble in a dynamically linked segmentation system.
a. Define a system that allows static linking and sharing of segments without requiring that the segment numbers be the same.
b. Describe a paging scheme that allows pages to be shared without requiring that the page numbers be the same.
Answer: Both of these problems reduce to a program being able to reference both its own code and its data without knowing the segment or page number associated with the address.MULTICSsolved this problem by associating four registers with each process. One register had the address of the current program segment, another had a base address for the stack, another had a base address for the global data, and so on. The idea is that all references have to be indirect through a register that maps to the current segment or page number. By changing these registers, the same code can execute for different processes without the same page or segment numbers.
9.16 Consider the following segment table:
Segment Base Length
0 219 600
1 2300 14
2 90 100
3 1327 580
4 1952 96
What are the physical addresses for the following logical addresses?
a. 0,430 b. 1,10
Answers to Exercises 37
c. 2,500 d. 3,400 e. 4,112 Answer:
a. 219 + 430 = 649 b. 2300 + 10 = 2310
c. illegal reference, trap to operating system d. 1327 + 400 = 1727
e. illegal reference, trap to operating system
9.17 Consider the Intel address translation scheme shown in Figure 9.20.
a. Describe all the steps that the Intel 80386 takes in translating a logical address into a physical address.
b. What are the advantages to the operating system of hardware that provides such complicated memory translation hardware?
c. Are there any disadvantages to this address translation system?
Answer:
a. The selector is an index into the segment descriptor table. The segment descriptor result plus the original offset is used to produce a linear address with a dir, page, and offset. The dir is an index into a page directory. The entry from the page directory selects the page table, and the page field is an index into the page table. The entry from the page table, plus the offset, is the physical address.
b. Such a page translation mechanism offers the flexibility to allow most operating sys-tems to implement their memory scheme in hardware, instead of having to imple-ment some parts in hardware and some in software. Because it can be done in hard-ware, it is more efficient (and the kernel is simpler).
c. Address translation can take longer due to the multiple table lookups it can invoke.
Caches help, but there will still be cache misses.
9.18 In theIBM/370, memory protection is provided through the use of keys. A key is a 4-bit quantity. Each 2K block of memory has a key (the storage key) associated with it. TheCPU also has a key (the protection key) associated with it. A store operation is allowed only if both keys are equal, or if either is zero. Which of the following memory-management schemes could be used successfully with this hardware?
a. Bare machine b. Single-user system
c. Multiprogramming with a fixed number of processes d. Multiprogramming with a variable number of processes
e. Paging f. Segmentation
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Answer:
a. Protection not necessary, set system key to 0.
b. Set system key to 0 when in supervisor mode.
c. Region sizes must be fixed in increments of 2k bytes, allocate key with memory blocks.
d. Same as above.
e. Frame sizes must be in increments of 2k bytes, allocate key with pages.
f. Segment sizes must be in increments of 2k bytes, allocate key with segments.