Mismatch Model

According to [15], the variance or standard deviation σg(x,y) of a function g(x,y) with two random variables x and y can be expressed as

^2g(x,y)

g

^{2 2x}

g

^{2 2y}

g g

^ov correlation coefficient between x and y. Thus the mismatch of the difference in the drain current ID can be written as function of the variances in the associated process parameters:

where , and are the coefficient of variance of the difference in

D, the body effect coefficient γ, and the flat-band voltage V_FB, respectively. To facilitate the analysis, we assume C_ov(V_FB,γ) = 0. This is a basic assumption in the field [18]-[20] since the process variations are independent of each other in nature. Note that the variations in the gate oxide thickness t_ox and channel effective doping concentration N_A are simultaneously reflected in the single parameter γ since γ includes both t_ox and N_A, i.e. γ = t_ox 2qε N_{si A} / ε_ox where ε_si and ε_ox are the silicon and oxide permittivities, respectively. The following weak inversion current expression is considered for the derivation of the model [16]:

intrinsic concentration. From (3.7) the derivatives in (3.6) can easily be derived:

V

^{th f B}

Apparently, (3.10) analytically expresses the current mismatch in weak inversion as function of the coefficient of variance of the difference in V_FB and γ.

Fig. 3.6(a) shows four different gate width with the same length and Fig.

3.6(b) shows the same width with three different length for the coefficient of variance versus I

ID

σ D.

Fig. 3.7 shows the measured drain current mismatch in weak inversion

versus the back-gate bias with seven different dimensions.

From Fig. 3.8(a) and (b) we can observe that the coefficient of variance in V_FB and γ each effectively follow the inverse square root of the device area, in agreement with [18], [19]. Thus empirically we have

= A

WL

γ

σ

γ _and ^FB

FB

V V

= A

σ WL

(3.11) where Aγ and are the size proportionality constants for and , respectively. The extracted values lead to A

VFB

A σ_γ

VFB

σ

γ = 0.013464µm and = 0.006441µm. Therefore, a combination of (3.10) and (3.11) can serve as an analytic design tool for properly calculating the mismatch with back-gate forward bias and device size both as input parameters.

VFB

A

Chapter 4 Conclusion

The current mismatch of a small gate area n-channel MOS transistor with its well-to-source junction forward and reverse biased has been extensively measured and analyzed. The n-channel MOS transistor with well-to-source junction slightly forward biased acts as a gated lateral bipolar transistor in low level injection. Our measured mismatch data for zero back-gate bias are close to the existing ones with comparable size. The measured data exhibit important observations: (i) back-gate reverse bias can make worse the mismatch in current; and (ii) current match can be substantially improved by the gated lateral bipolar action. The measured dependencies of the mismatch on the well-to-source forward and reverse biases have been successfully reproduced by a new simple statistical model.

The new simple mismatch model has successfully reproduced the extensively measured data. The extracted variations in the associated process parameters have been found to follow the inverse square root of the device area. The work of optimizing the trade-off between the match and the device size with back-gate forward bias as design parameter has been demonstrated based on the model.

References

[1] E. A. Vittoz, “Micropower techniques,” in Design of MOS VLSI Circuits for Telecommunications, Y. Tsividis and P. Antognetti, Eds., Prentice-Hall, Inc., NJ. pp. 104-144, 1985.

[2] A. Pavasovic, Subthreshold region MOSFET mismatch analysis and modeling for analog VLSI systems, Ph. D. Dissertation, the Johns Hopkins University, 1990.

[3] F. Forti and M. E. Wright, “Measurement of MOS current mismatch in the weak inversion region,” IEEE J. Solid-State Circuits, vol. 29, pp.

138-142, Feb. 1994.

[4] M. D. Godfrey, “CMOS device modeling for subthreshold circuit,”

IEEE Trans. Circuits and Systems-II: Analog and Digital Processing, vol. 39.

pp. 532-539, Aug. 1992.

[5] E. A. Vittoz, “The design of high-performance analog circuits on digital CMOS chips,” IEEE J. Solid-State Circuits, vol. SC-20, pp. 657-655, June. 1985.

[6] L. Watts, D. A. Kerns, R. F. Lyon, and C. A. Mead, “Improved implementation of the silicon cochlea,” IEEE J. Solid-State Circuits, vol. 27,

[7] C.A. Mead Analog VLSI and Neural Systems, Addison-Wesley Co., MA., 1989.

[8] S. Verdonckt-Vandebroed, S. S. Wong, J. C. S. Woo, and P. K. Ko

“High-gain lateral bipolar action in a MOSFET structure,” IEEE Trans.

Electron Devices, vol. 38, pp. 2487-2496, Nov. 1991.

[9] T. H. Huang and M. J. Chen, “Empirical modeling for gate-controlled collector current of lateral bipolar transistors in an n-MOSFET structure,”

Solid-State Electronics, vol. 38, pp. 115-119, Jan 1995.

[10] T. H. . Huang and M. J. Chen, “Base current reversal phenomenon in a CMOS compatible high gain n-p-n gated lateral bipolar transistor,” IEEE Trans. Electron Devices, vol. 42, pp. 321-327, Feb. 1995.

[11] E. A. Vittoz, “MOS transistors operated in the lateral bipolar mode and their application in CMOS technology,” IEEE J. Solid-State Circuits, vol. SC-18, pp. 273-279, June. 1983.

[12] T. W. Pan and A. Abidi, “A 50-db variable gain amplifier using parasitic bipolar transistors in CMOS,” IEEE J. Solid-State Circuits, vol. 24, pp. 951-961, Aug 1989.

[13] Y. P. Tsividis, Operation and Modeling of the MOS Transistor, McGraw-Hill Co., N.Y. 1987.

[14] P. Antognetti, D Caviglia, and E. Profumo, “CAD model for threshold

and subthreshold conduction in MOSFET’s,” IEEE J. Solid-State Circuits, vol. SC-17, pp. 454-458, June. 1982.

[15] A. Papoulis, Probability, Random Variable and Stochastic Processes, Tokyo: McGraw-Hill, Kogakusha, 1965.

[16] M. J. Chen, J. S. HO, and T. H. Huang, “Dependence of Current Match on Back-Gate Bias in Weakly Inverted MOS Transistors and Its Modeling,” IEEE J. Solid-State Circuits, vol. 31, pp. 259-262, Feb.1996.

[17] E. A. Vittoz, “Low-power design: ways to approach the limits,” IEEE 1994 International Solid-State Circuits Conference, Digest of Technical Papers, pp. 14-18.

[18] K. R. Lakshmikumar, R. A. Hadaway, and M. A. Copeland,

“Characterization and modeling of mismatch in MOS transistors for precision analog design,” IEEE J. Solid-State Circuits, vol. 21, pp.

1057-1066, Dec. 1986.

[19] M. J. M. Pelgrom, A. C. J. Duinmaijer, A. P. G. Welbers, “Matching properties of MOS transistors,” IEEE J. Solid-State Circuits, vol. 24, pp.

1433-1440, Oct. 1989.

[20] C. Michael and M. Ismail, “Statistical modeling of device mismatch for analog MOS integrated circuit,” IEEE J. Solid-State Circuits, vol. 27, pp.

154-165, Feb.1992.

Fig. 2.1 The used dies on wafer. All dies on wafer contain many n-channel MOS transistors with the same structure.

0.0 0.2 0.4 0.6 0.8 1.0 1.2

10^-8 10^-7 10^-6 10^-5

W=1µm L=0.5µm V_D=0.01V

I D (A)

V_GS(V)

V_BS= -0.8V V_BS= -0.4V V_BS= 0V V_BS= 0.4V

Fig. 2.2 The drain current versus gate voltage characteristics with back-gate bias as parameter from one of 25 n-channel

MOSFETs in one die.

0.0 0.2 0.4 0.6 0.8 1.0 1.2 10^-8

10^-7 10^-6

W=1µm L=0.5µm V_D=0.01V

I D (A)

V_GS (V)

V_BS = -0.8V V_BS = 0V V_BS = 0.4V

Fig. 2.3 The measured drain current versus gate voltage characteristics for three different back-gate biases.

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 with three different V .

10^-10 10^-9 10^-8 10^-7 10^-6 0

10 20 30 40 50

σ ID(%)

I_D (A)

W/L=1µm/0.1µm W/L=1µm/0.5µm W/L=1µm/1µm

Fig. 3.2 The versus the drain current for zero back-gate bias.

ID

σ

10^-10 10^-9 10^-8 10^-7 10^-6 0

5 10 15 20 25 30

35 W=1µm L=0.5µm V_D=0.01V

V_BS= -0.8V V_BS= -0.4V V_BS= 0V V_BS= 0.4V

σ ID(%)

I_D(A)

Fig. 3.3 The measured drain current mismatch versus the drain current with the back-gate bias as parameter.

-0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 22

24 26 28 30 32

VFB

2.767 % 1.018 % σγ =

σ =

I_D = 10^-9A I_D = 3x10^-9A

W=1µm L=0.5µm V_D=0.01V

σ ID (%)

V_BS(V)

Fig. 3.4 The measured drain current mismatch in weak inversion versus the back-gate bias for two different drain currents. The calculated results from Eq. (2.4) are also shown for comparison.

0.0 0.2 0.4 0.6 0.8 1.0 1.2

10^-8 10^-7 10^-6

10^-5 W=1µm L=0.5µm V_D=0.01V

I D (A)

V_GS(V)

V_BS= -0.8V V_BS= -0.4V V_BS= 0V V_BS= 0.4V

Fig. 3.5 The drain current versus gate voltage characteristics with back-gate bias as parameter.

10^-9 10^-8 10^-7 10^-6 10^-5

Fig. 3.6(a) Four different gate width with the same length for the coefficient of variance versus I

ID

σ D.

10^-10 10^-9 10^-8 10^-7 10^-6

Fig. 3.6(b) The same width with three different lengths for the coefficient of variance versus I

ID

σ D.

-0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4

Fig. 3.7 The measured drain current mismatch in weak inversion versus the back-gate bias with seven different dimensions.

0 1 2 3 4 0

1 2 3 4 5

σ = Α WL

Α =0.013464µm

γ γ

γ

σ γ (%)

1/ WL (1/µm)

Experiment

Fig. 3.8(a) The measure and calculated σ versus the inverse square root _γ of the device area.

0 1 2 3 4 5

Fig. 3.8(b) The measure and calculated versus the inverse square root of the device area.

VFB

σ

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