Model Description Introduction

The schematic of the 3-D quadruple-gate (QG) MOSFETs is shown in Fig. 3.3.1(a).

Figs. 3.3.1(b) and 3.3.1(c) are the two-dimensional (2-D) device structure to derive the model. With various trapped charge distributions, the channel can be divided into three regions. Regions 1 and 3 denote undamaged zone. Region 2 is damaged zone. 3-D simulations are computationally more expensive and are not acceptable for compact modeling in comparison to 2-D simulations. To avoid solving for 3-D Poisson equation, 3-D QG device can be genuinely replaced with the two 2-D equivalently symmetric double-gate structures.

Fig. 3.3.1 Schematic of quadruple-gate MOSFETs: (a) three-dimensional device structure. With cut plane x direction and y direction, the device can be equivalently composed of 2 two-dimensional symmetrical double-gate (SDG) MOSFETs with width of W as shown in (b) with width of H as shown in (c). The two-dimensional device structures of Fig. 3.3.1 (b) and Fig. 3.3.1 (c) are used to derive the model, where regions

3.3.3 2-D Generalized Potential Model

The coupling effects between 2-D equivalently asymmetric and symmetric double-gate structures can be ignored by the fact that channel length (Lg)/channel width (W) and channel length (Lg)/channel thickness (H) are larger than 2, which fall within the restrictions required to obtain realistic and operational QG devices [8]. Since the most leaky path is along the in the middle of the channel for the 3-D QG device (i.e., at the position of (x=W/2, y=H/2, z), the 3-D potential of Φ(x=W/2, y=H/2, z) can be equivalently decomposed of 2-D central potential of Φ(x=W/2, z) for 2 symmetrical double-gate (SDG) MOSFET.

Based on the exact two-dimensional (2-D) solution of Poisson equation, the central potential Φc,i(z) (i=1,2,3) for SDG MOSFET can be expressed as

( )

1 2

where ξ, τ and κ in above equations are defined as

( ) ( ) ^{( )}

The analytical potential model for symmetrical trapped-charge double-gate devices (i.e. Φi,sym1(x,z) and Φi,sym2(gyms), i=1,2,3) have been developed. By using the perimeter-weighted-sum method, that treats trapped-charge QG device as separate devices operating in parallel, the analytical potential for the trapped-charge QG MOSFETs can be obtained as the perimeter-weighted sum of the analytical potential for two symmetrical trapped-charge QG device. Accordingly, the analytical potential for the trapped-charge QG device can be defined by

i( , , )x y z ,_sym1,i( , )x z _sym ,_sym2,i( , ) (1y z _sym) (i 1,2, and 3)

φ =φ ×α +φ × −α = (3.3.19)

where φ_i( , , )x y z is the analytical potential in region 1, 2 and 3 for QG device,φ_,sym1,i( , )x z ^,φ_,sym2,i( , )y z are the analytical potential in region 1, 2 and 3 given by eq.(3.3.1)-eq.(3.3.3) for symmetrical double-gate (SDG) devices, and αsym is the ratio of symmetrical double-gat (SDG) MOSFETs to the entire QG MOSFETs by eq.(3.2.2).By using scaling theory,k and _n θ_n are given by eq.(3.2.4) and eq.(3.2.5), respectively.

Na is the uniform doping concentration of the silicon film, tox is the gate oxide thickness , H is the silicon film thickness, εsi is the dielectric constant of silicon (εsi=11.7×8.85×10^-14 ), εox is permittivity of oxide (εox=3.9×8.85×10^-14), Vgs is the top gate bias and Vfb1=Vfb3 is the flat-band voltage in the undamaged regions. In the damaged region, due to the effect of equivalent oxide charges on the flat-band voltage, we get V_fb2 from eq.(2.2.18).

To verify the proposed model, the published 3-D device simulator, “DESSIS”, is performed to simulate the device. Fig. 3.3.2 shows the dependence of channel potential on the normalized channel position for the different ratios of damaged zone to undamaged zone. As the length of the damaged zone increases, the deformation of the potential barrier increases. In the case of the negative interface fixed charges, the minimum bottom potential appears in the damaged zone, whereas in the case of the positive interface fixed charges, it appears in the undamaged zone. This implies that a large Vth shift would be observed in the former case. Fig. 3.3.3 and Fig. 3.3.4 show the dependence of potential distribution on both of the channel length and channel height with the damaged and fresh devices for the simulation and the model results. The good match between the simulation and model results is obtained. It is shown that the damaged device with positive trapped charges will decrease the potential barrier between the source and drain side in comparison to the fresh device. It will increase the threshold voltage degradation of the fresh device. On the other hand, the device with the negative trapped charges will increase the potential barrier between the source and drain side (i.e., increasing DIBL). It will decrease the threshold voltage degradation of the fresh device (i.e., decreasing DIBL).

0 0.2 0.4 0.6 0.8 1

Fig. 3.3.2 The dependence of channel potential on the normalized channel position for the different ratios of damaged zone to undamaged zone.

Fig. 3.3.3 The variation of the two-dimensional potential distribution with the channel length and channel height for the simulation (The blue plot is for the damaged device with the positive trapped charges, the green plot is for the fresh device, and the red plot is for the damaged device with the negative trapped charges).

Fig. 3.3.4 The variation of the two-dimensional potential distribution with the channel length and channel height for the model results (The blue plot is for the damaged device with the positive trapped charges, the green plot is for the fresh device, and the red plot is for the damaged device with the negative trapped charges).

3.3.4 Threshold Voltage Model

As mentioned in chapter 3.1, the most popular Vth definition used in compact modeling is the gate voltage φB at which the band bending reaches at the silicon surface, where φB is the difference between the Fermi level and intrinsic level of silicon in the neutral region. Under this condition, the inversion carrier density at the silicon surface equals the density of the doping atoms in the silicon bulk Na. This definition has been physically reasonable and successful in identifying the turn-on condition for bulk devices, where Na -values are in the range of 1×10¹⁶cm^-3.

In order to solve analytical threshold voltage, we need to rewrite coefficients as a linear equation related to Vgs. From eq.(3.3.4-3.3.13), we get

,1 gs ,2

'_i=1 1,2,3 Due to rapid decay of the Fourier series coefficients as shown in eq.(3.3.14)-eq.(3.3.18) and eq.(3.3.20)-eq.(3.3.45), the first term of them can dominate the whole series, and the minimum potential as a linear equation related to gate bias (Vgs) of the silicon body for region 1-3 can be expressed as:

2

Using eq.(3.3.46)-eq.(3.3.48) and Фmin=2φB, respectively, we can get three quadratic equations in region 1-3 as:

2

From eq.(3.3.49)-eq.(3.3.51), and solving for Vgs, the threshold voltage can be Finally, by the perimeter-weighted-sum approach [24] that treats Quadruple-gate (QG)MOSFET as separate devices operating in parallel, the threshold voltage for the Quadruple-gate (QG) MOSFETs can be obtained as the perimeter-weighted sum of the threshold voltages for both two SDG MOSFETs. From eq.(3.3.59)-eq.(3.3.61),this leads to

, , 1, , 2, (1 ) ( 1,2, and 3)

th i th sym i sym th sym i sym

V =V ×α +V × −α i= (3.3.62)

Where αsym eq.(3.2.2) is the ratio of SDG MOSFET to the entire Quadruple-gate (QG) MOSFET, which can be 1 (if W<<H) for pure SDG MOSFET device and can be 0 (if W>>H) for genuine SDG MOSFET. For Quadruple-gate (QG) MOSFETs device, one obtains 0<αsym<1.

Fig. 3.3.5 shows how the threshold voltage degradation is affected by the normalized damaged zone for the different silicon thicknesses. The increased damaged zone can further degrade the threshold voltage by reflecting the effects of the localized negative/positive trapped charges on the threshold voltage degradation. This interface trapped charge induced threshold voltage degradation is called “ITTVD”. For the positive trapped charges, large thickness of H=40 nm will suffer more ITTVD than the small one of H=20 nm when Ld is increased. However, the large thickness of H=40 nm with negative trapped charges will suffer less ITTVD than the small thickness of H=20nm until the normalized damaged zone of Ld/Lg is increasing beyond 0.5 (called critical ratio of damaged zone to the channel region denoted by CR(5,10)≈0.5). In other words, to resist ITTVD caused by the negative trapped charges, the larger H is preferred only if CR<0.5. Fig. 3.3.6 shows the dependence of threshold voltage degradation on

the normalized damaged zone for different gate oxide thicknesses. The localized trapped charges with large normalized damaged zone will cause great threshold voltage degradation, especially for the thick oxide thickness. To reduce ITTVD, not only the thin gate oxide should be accounted for, but also the small damaged zone must be desired for the device.. Fig. 3.3.7 depicts the dependence of the threshold voltage roll-off on the gate length for both damaged and fresh devices. The ITTVD may be coupled with the DIBL. Since the ITTVD caused by the negative trapped charges (i.e., threshold voltage roll-up as shown in Figs. 3.3.5-3.3.6) has an opposed effect to DIBL, the threshold voltage roll-off for the negative trapped-charge device will be decreased and become less than that for the fresh device when the channel length is decreased. On the contrary, the ITTVD caused by the positive trapped charges (i.e., threshold voltage roll-off as shown in Figs. 3.3.5-3.3.6) takes the same effect as DIBL and the threshold voltage roll-off for the positive trapped-charge device will be enhanced and become more than that of the fresh device. Although the negative trapped charge can alleviate DIBL, it will bring about the large threshold voltage. This could be an obstacle for the low-voltage circuit application. It should be pointed out that if both Lg/H <2 and Lg/W<2, the coupling effects between two symmetrical double-gate MOSFETs can not be negligible [8] and it can cause the large discrepancy between the model and numerical simulator. This clearly explain why when channel length is further reduced toward into 40 nm in Fig. 3.3.7, both Lg/H <2 and Lg/W<2 will yield the large deviation between results of the analytical model and those of 3-D numerical simulation. 2-D model can accurately predict the threshold voltage of QG transistor as long as Lg/H >2 and Lg/W>2. Otherwise, 3-D model is required to simulate the QG device accurately.

With the better control of SCEs than the planar MOSFETs, the advanced non-planar multi-gate (MG) MOSFETs such as the double-gate (DG), tri-gate (TG), and quadruple-gate (QG) MOSFETs are the more attractive devices for the nanometer MOSFET application. Fig. 3.3.8 shows the threshold voltage degradation versus the normalized damaged zone for the double-gate (DG), tri-gate (TG), and quadruple-gate (QG) MOSFETs. For the negative trapped charges, TG MOSFET offers the best immunity to ITTVD in compared with DG and QG MOSFETs. For the positive trapped charges, DG MOSFET will experience the most ITTVD in three devices. It is interesting to note that QG MOSFET can more effectively suppress ITTVD only when Ld/Lg<0.8 in comparison to DG and TG MOSFETs for the positive trapped charges. For

the negative trapped charges, QG MOSFET will give rise to the most ITTVD among the three devices.

It should be pointed out that although the quantum mechanical effects (QM) is not accounted for in the work, it has been derived in the previous literatures [26] that QM will pull up the threshold voltage since the quantum mechanical channel potential barrier is larger than classical channel potential barrier, which will increase the gate voltage for inverting the channel. It can be concluded that the threshold voltage in Fig.3.3.7 will shift upward in parallel by considering QM. The corner inversion effects [27] that induce independent channels with different threshold voltages in the QG MOSFETs can be negligible in the model due to Lg/H >2 and Lg/W>2 that will cause almost the same potential between the surface and the corner for the device [28].

0 0.2 0.4 0.6 0.8 1

Normalized Damaged Zone, L_d/L_g -0.3

Dash Line : Damaged device with -Nf Solid Line : Damaged device with +Nf

& : H=W= 20nm , : H=W= 30nm - : H=W= 40nm

Line : Model Symbol : DESSIS

Fig. 3.3.5 Threshold voltage degradation versus normalized damaged zone for different thicknesses of silicon body.

0 0.2 0.4 0.6 0.8 1 Normalized Damaged Zone, L_d/L_g

-0.5

Dash Line : Damaged device with - Nf Solid Line : Damaged device with +Nf

& : tox=1 nm , : tox=3 nm - : tox=5 nm

Line : Model Symbol : DESSIS

Fig. 3.3.6 Threshold voltage degradation versus normalized damaged zone for different thicknesses of gate oxide.

Fig. 3.3.7 Threshold voltage roll-off versus gate length for both fresh and damaged devices.

0 0.2 0.4 0.6 0.8 1 Normalized Damaged Zone, L_d/L_g

-0.25

Solid Line : Damaged device with +Nf Dash Line : Damaged device with - Nf

& : Quadruple-Gate , : Triple-Gate - : Double-Gate

Line : Model Symbol : DESSIS

Fig. 3.3.8 Threshold voltage degradation versus normalized damaged zone for DG, TG, and QG MOSFETs.

3.3.5 Subthreshold Currrent Model

By accounting for the effects of equivalent oxide charges on the flat-band voltage, a novel interface-trapped-charge-induced subthreshold current model is presented for the quadruple-gate (QG) MOSFETs based on the 3D scaling equation and Pao-Sah’s integral. It indicates that a thin gate oxide can effectively reduce the subthreshold current degradation caused by the trapped charges. In contrast to the thin gate oxide, a thick silicon film is required to alleviate the subthreshold current degradation caused by the negative trapped charges.

The current density primarily flows from the drain to the source and consists of both terms of drift current and diffusion current. Supposed that the current density flows through virtual z=zmin, then the general subthreshold current for the DG MOSFETs can be expressed as

min, min, In the SOI MOSFETs device, the subthreshold leakage mainly occurs in the virtual cathode point zmin.

Base on two dimensional Poisson’s equation and perimeter-weighted-sum method, a new analytical subthreshold current model for trapped-charge QG MOSFETs is successfully developed in this section. By using the perimeter-weighted-sum method for QG MOSFETs, the subthreshold current IDG,sym1,i and IDG,sym2,i is considered to describe the subthreshold current IQG,d,i in the QG MOSFET. Accordingly, the subthreshold current can be expressed as

, ,( , , ) , 1, ( , ) , 2, ( , ) (1 )

QG d i DG sym i sym DG sym i sym

I x y z =I x z ×α +I y z × −α (3.3.64)

with

where IQG,d,i is the subthreshold current for trapped-charge QG device, IDG,sym1,i and IDG,sym2,i are the subthreshold currents given by eq.(3.3.63) for symmetrical trapped-charge double-gate.

Interface-Trapped-Charges-Induced Subthreshold Current Degradation

(ITSUBD=log[Ids,damaged]-log[Ids,fresh]) is defined by the difference between the fresh and damaged devices for their subthreshold currents in logarithm scales. With the fixed positive/negative trapped charges, Fig. 3.3.9 plots ITSUBD versus normalized damaged zone Ld/Lg for different silicon film thicknesses. Increased the Ld/Lg can further enhance ITSUND for both positive and negative trapped charges. A thick silicon film of H=40 nm is desirable for reducing the ITSUBD caused by the negative trapped charges. On the contrary, a thin silicon film, such as H=20 nm is required to suppress ITSUBD caused by the positive trapped charges. Fig. 3.3.10 shows ITSUBD with Ld/Lg for different gate oxide thicknesses. Irrespective of the polarities for the trapped charges, tox=1 nm induces a smaller ITSUBD than tox=3 nm and 5 nm. Although a thin gate

oxide is needed to make the device suffer less ITSUBD, it may initiate the oxide leakage current due to the tunneling effects, which will cause the static power consumption. The trade-off regarding how to reduce ITSUBD without inducing the gate leakage current caused by the tunneling effects should be taken into account as the thin gate device is applied for memory circuits. Fig.3.3.11 plots subthreshold current roll-up versus the gate length for damaged and fresh devices. The subthreshold current roll-up (SUBRUP) is defined by the difference between the long-channel and short-channel devices for their subthreshold currents in logarithm scales. (i.e., SUBRUP

=log[Ids,short]-log[Ids,long]). As the gate length is reduced, the damaged device with negative trapped charges suffers less short-channel effects (SCEs) and has a smaller SUBRUP than the fresh device. In contrast to the negative trapped charges, the positive trapped charges can enhance SCEs and cause the damaged device more SUBRUP than the fresh device when the gate length is further decreased.

Fig. 3.3.9 ITSUBD versus normalized damaged zone for different silicon body thicknesses.

Fig. 3.3.10 ITSUBD versus normalized damaged zone for different gate oxide thicknesses.

Fig. 3.3.11 SUBRUPversus gate length for the fresh and damaged devices.

3.3.6 Results and Discussion

The hot-carrier effects (HCEs) that bring about the accumulated interface trapped charges will degrade the device/circuits performance. The generic mechanism of the hot-carrier-induced trapped charges was revealed in the previous literatures. It indicates that the device/circuits degradation with the trapped charges is mainly caused by accumulated dc stress under the condition that the gate voltage is near the threshold voltage and the high drain voltage, i.e., the drain-avalanche hot-carrier (DAHC) stress condition. In other words, the damaged zone and the interface positive/negative trapped charges can be attributed to DAHC. A numerous of literatures have modeled the hot-carrier-induced threshold voltage of planar and double-gate MOSFETs in the past decade. Until now, there is no thesis to investigate the subthreshold behavior model of the QG MOSFETs including the localized interface trapped charges. With the strong field confinement, prominent volume conduction, and high packing density, the QG MOSFETs that have demonstrated improved short-channel immunity and high driving currents can be used for memory cells. Also, QG MOSFETs showing the better scaling length are more promising than both planar and double-gate MOSFETs for the future VLSI circuits. In this work, by considering effects of equivalent oxide charges on the flat-band voltage, effective conducting path, and Poisson equation, a novel analytical subthreshold behavior model for QG MOSFETs with the interface trapped charges including threshold voltage is developed. The model thoroughly investigates the effect of localized trapped charges with the different polarities, damaged zones, oxide thicknesses, and channel widths/thicknesses on the threshold voltage degradation. When ITTVD is prominent and coupled with short short-channel effects, the positive/negative interface trapped charges can increase/decrease threshold voltage degradation caused by DIBL. Besides, the thin oxide will improve the threshold voltage behavior when the interface charges are presented and the damaged zone is increased. Instead of small thickness of silicon film, a large thickness of silicon body is required to resist the ITTVD when the negative interface trapped charges are presented. The proposed model is verified by the three-dimensional (3-D) numerical simulation and explicitly illustrates how the trapped charge density with different polarities, damaged zone, oxide thickness, and silicon thickness affect the threshold voltage characteristics.

C ^hapter 4

T HREE DIMENSIONAL SUBTHRESHOLD BEHAVIOR MODEL FOR Quadruple-GATE (QG) SOI MOSFETs with/without Localized

Trapped Charges

4.1 Three Dimensional Subthreshold Behavior Model for SOI Quadruple -Gate MOSFETs

4.1.1 Model Derivation

A schematic view of the three-dimensional quadruple-Gate (QG) MOSFETs is shown in Fig. 4.1.1, where H is the silicon body thickness, W is the channel width, and L is the channel length. The gate electrode surrounds the silicon body with a gate oxide thickness tox. The body of the silicon is doped with acceptor concentration Na. The gate material is metal which has a proper work function to adjust the threshold voltage

We consider the same assumption as the 2-D model that impurity density Na in the channel region is uniform independent of the gate length and neglecting the effect of the fixed oxide charges on the electrostatics of the channel. The channel potential distribution is expressed by Φ( , )x z . According to the Poisson equation, the channel potential distribution can be written as eq.(4.1.1).

( ) ( ) ( )

2 2 2

2 2 2

, , , , , , _a

si

x y z x y z x y z qN

x y z

φ φ φ

ε

∂ ∂ ∂

+ + =

∂ ∂ ∂ (4.1.1)

Fig. 4.1.1 The three dimensional (3-D) structure for QG SOI MOSFETs

Where Na is the uniform doping concentration of the silicon film, tox is the gate oxide thickness, W is the silicon film width, Lg is the device channel length, and the x-axis is perpendicular and the z-axis is parallel to the channel length, respectively.

By using the superposition method, the resultant solution φ( , , )x y z can be composed with one-dimensional (1-D) potential solution V(x) , 2-D potential solution U(x,z) and 3-D potential solution ψ( , , )x y z which satisfy the following 3-D Laplace equation, 2-D Laplace equation and 1-D Poisson equation, respectively.

( , )x z V x( ) U x z( , )

Φ = + +ψ( , , )x y z (4.1.2)

Substituting eqns.(4.1.2) into eqns.(4.1.1), we obtain

4.1.2 3-D Boundary Conditions Value Problem

The Poisson equation is solved by using the following boundary conditions:

The Poisson equation is solved by using the following boundary conditions: