Chun-Kai Wang and Che-Sheng Chen Department of Electronic Engineering
National Chiao Tung University Hsinchu 300, Taiwan
E-mail: [kernzip, chen.chesheng]@gmail.com
Kuei-Ann Wen
Department of Electronic Engineering National Chiao Tung University
Hsinchu 300, Taiwan E-mail: [email protected]
Abstract—A monolithic CMOS MEMS capacitive accelerometer with micropower analog readout circuit is presented in this paper. In order to optimize noise-power performance of accelerometer in limited area, a specification driven MEMS/IC co-design flow is adopted. In analog readout circuit design, the proposed circuit architecture combines chopper stabilization and correlated double sampling to suppress low frequency noise and compensate DC offset. The RMS input referred noise voltage is 9.82 nV/√Hz under 100Hz. The power consumption is 36uW at 100kHz modulation frequency.
I. INTRODUCTION
CMOS MEMS accelerometers are applied for a wide range of applications, including automotive safety, virtual reality, movement detection, various navigation system, and mobile devices. A CMOS MEMS accelerometer has the advantages of low temperature coefficient, low power dissipation, low noise, and low cost due to it’s compatibility with wafer fabrication process. However, monolithic CMOS MEMS accelerometers fabricated with standard ASIC process have very small sensing capacitance, of which the differential relative variation usually on the order of
17F
18~10
10− − within the bandwidth ranging from several Hz to several hundred Hz, and that cause low mechanical sensitivity. Therefore, the main design consideration is how to suppress low frequency noise and DC offset in readout circuit design. Furthermore, for wireless devices and portable consumer electronics devices, the power dissipation is another critical design consideration for the capacitive sensing sensors.
One of the readout circuits widely used in CMOS MEMS accelerometers is switched-capacitor (SC) charge integration method [1]. The correlated double sampling (CDS) technique has been used to significantly reduce the DC offset and low frequency noise. The main drawback of the SC circuit is the related high kT/C noise with small feedback capacitor. The other one of the readout circuits is continuous-time voltage (CTV) method [2] [3]. The chopper stabilization (CS) tech-nique is employed to reduce the DC offset and low frequency noise. Both of the two noise reduce techniques could be integrated into one capacitive sensing readout circuit [4] [5]
[6]. However, the low noise readout circuits consume a power of few mW, and the low power readout interface circuits generate a noise of a few hundred μg/√Hz.
This paper presents both the readout circuit and a CMOS MEMS accelerometer. In accelerometer design, a specification driven MEMS/IC co-design flow is proposed. Low noise and compact accelerometer could be achieved. The proposed read-out circuit combines the chopper stabilization technique and the correlated double sampling to reduce low frequency noise and DC offset.
II. CIRCUIT ARCHITECTURE
The architecture of the CMOS MEMS accelerometer is shown in Fig. 1, where the fully differential capacitive bridge represents the sensing capacitors of the CMOS MEMS accelerometer. The design goal is to achieve 12-bit resolution under 1.2V peak to peak output swing with ±4g sensing range.
The bandwidth of the CMOS MEMS accelerometer is up to 100Hz. At the beginning, the output noise voltage should be less than half the LSB, i.e. 14.6μV/√Hz for 100Hz bandwidth.
The sensitivity could be 150mV/g due 1.2Vpp with ±4g sensing range. Assume the voltage swing at sensor output is 1mV/g, the voltage gain readout circuit can be obtained as 44 dB.
Figure 1. Architeture diagram of the readout circuit.
Considering noise and linearity, the voltage gain of the second stage amplifier is set to be 22dB. The gain of the first
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stage amplifier with the CDS circuit is 22dB. The input-referred noise is 97.3nV/√Hz. Because low noise circuit design is more easily to be achieved than MEMS design, the noise constrain of readout circuit is set to one fourth of total noise.
III. SPECIFICATION-DRIVEN MEMS/ICCO-DESIGN FLOW A specification-driven accelerometer design flow is proposed in this work. The target of this design flow is to find the minimum occupied area of accelerometer under required system performance. The geometry of 1-D accelerometer [7]
and simplified lumped model is shown as Fig. 2. The accelero-meter could be divided into three parts: spring, sensing fingers and proof mass. In order to minimize the area of the accelero-meter, the relationship between geometry parameters and mechanical properties should be found first.
(a) (b)
Figure 2. (a)Schematic of accelerometer and (b)lumped paramter model of accelerometer
The differential equation of displacement and external acceleration of sensor is given by
maext
where m is the mass of proof mass, x is the displacement of accelerometer, b is the damping coefficient and k is the stiffness of spring. With the 1st order approximation, the equation of displacement can be simplified as
2 n
aext
x=ω (2)
Based on (2), the resonant frequency ωn of sensor can be defined by the maximum displacement at maximum sensing gravity. For example, with 4um gap process constrain, the resonate frequency is 4.98kHz with 1% displacement at 1g (g:
gravity). With the maximum displacement, the maximum voltage swing at sensor output could be found as
swing of modulation signal and d is the gap between two fingers. The sensing capacitance Cs can be expressed as
d Nlt
Cs= εair/ (4) where N is the number of fingers, l is the finger length and t is the thickness of each finger. From (3) and (4), the larger area of fingers, the higher voltage swing at sensor output node with fixed parasitic capacitor. However, CS is limited by noise constrain of sensor. The Brownian noise of accelerometer can be expressed as
m temperature, b is damping factor and m is the weight in kg of proof mass. In capacitive accelerometer, squeeze film damping is the main contributor of damping factor. The squeeze film damping is shown as
3 atmospheric pressure at room temperature. From (6), we can find the damping factor is proportional to sensing capacitance with fixed thickness and gap. In order to achieve low noise performance, the sensing capacitance should be limited and the proof mass should as large as possible. However, the sensing capacitance should be large enough to meet sensitivity constrain. Therefore, the minimum occupied area could be found under these constrains. The MEMS/IC co-design flow as illustrated in Fig. 3 is adopted for accelerometer and read-out performance evaluations.
Sensitivity > 1mV/g
Brownian noise
<0.75 Total noise
Circuit design Electrical noise<Total noise/4
Set Id1=1uA
Design Gain Bandwidth Setup chopper frequency
Electrical flicker noise<Total noise/8
Get MOSs W/L ratio for readout circuit goal
Yes No
(WL)1=(WL)1L+1 Cs=1fF, set Cp~150fF
Get damping coefficient b from Cs Proof mass m=1 nano-gram
Yes
Figure 3. MEMS/IC co-design flow
noise coefficient which is typically ten times lower than NMOS FETs. The mean square equivalent input noise could be expressed as below
g f
where T is absolute temperature, W and L are the dimensions of MOSFETs, Cox is the gate capacitance per area, f is frequency, Kfp is the PMOS flicker noise coefficient, Kfn is the NMOS flicker noise coefficient, and gm is transconductance.
From (7), the larger size of MOSFET, the lower flicker noise of MOSFET. On the other side, parasitic capacitance at input node of amplifier will be larger. However, based on (3), large parasitic capacitance will degrade the sensitivity of sensor.
Another design parameter for low noise is the transcon-ductance. Large transconductance of input MOSFET will suppress noise level but also consume more current.
Figure 4. Schematic of the 1st stage amplifier.
To simplify the design flow, gm3/gm1 and gm5/gm1 are set to less than 0.1 then the noise contribution of MOSFET 3~6 could be negligible. Based on (3), Cp is set to 150fF for acceptable CS. Because it easier to design low noise circuit than MEMS accelerometer, the electrical noise is set to one fourth of total system noise. The size of MOSFET could be found from (7) by increasing bias current slightly until meet the noise specification. The buffer is used to drive loading capacitors of CDS circuit.
B. Chopper Stabilization Technique
The principle of chopper stabilization is illustrated in Fig.
5. The approach applies modulation to transpose the signal to the chopper frequency, while the noise is unaffected. After the second multiplier, the signal is demodulated back to the original one, and the offset and noise has been modulated to the chopper frequency. This chopping operation results in and equivalent input noise spectrum that is shown in Fig. 5, where the offset and noise signal has been shifted to the odd harmonic frequencies of the chopper frequency. A low-pass filter can be used to reduce the amplitude of the offset and noise. Therefore, if the chopper frequency is much higher than the signal bandwidth, the flicker noise will be greatly reduced with this technique.
A1
Figure 5. Concept of chopper stabilization technique.
C. Corrected Double Sampling Technique
The correlated double sampling technique is used to subtract out error voltage with two sequential samples. The technique is illustrated in Fig. 6.
Figure 6. Schematic of correlated double sampling.
During phase one, Ccds is charged to the output. During the complementary phase, the output drives the series of the pre-charged Ccds. Due to the input chopping, the output voltage Vo is where Verror is the offset and the flicker noise. By inspection of Fig. 6, during Φ1, we have
cds o
cds V C
Q (1)=− (1) . (10) Therefore, duringΦ2, the voltage across Ccds becomes
in that is showing that the Verror is subtracted by CDS. The output of the first stage amplifier is differential. Therefore, the complete scheme of the method as shown in Fig. 6 can be realized that uses two CDS structures working on both outputs.
The 2kT/C noise of the output sampling is negligible compared to the input divided byA12.
D. Second Stage Amplifier
The second stage amplifier is the folded cascade amplifier as shown in Fig. 7. An input with PMOS FETs is used due to lower flicker noise coefficient. The differential offset inputs are designed for compensating the sensor structure mismatch.
Large capacitance can reduce the unit gain frequency and increase the phase margin. For the circuit architecture, the close loop amplifier of the second stage amplifier could be used as a low pass filter to remove the modulated noise signal.
The second stage amplifier offers the gain of Ca/Cc.
Vdd Vdd
Figure 7. Schematic of folded cascode amplifier.
V. SIMULATION RESULTS
The proposed readout circuit and CMOS MEMS accelero-meter is implemented by TSMC 1P6M 0.18um CMOS mix-signal technology. The readout circuit operates with supply voltage 1.8V. The circuit is simulated in Cadence design environment using Spectre simulator. The chopper frequency is 100kHz. The designed open loop gain of the second stage amplifier is 70.75dB. It achieves a 129Hz unit gain band-width with a 88° phase margin at a 10nF load. The input signal of readout circuit is ±4mV with ±4g sensing voltage.
The noise simulation is achieved by periodic noise analysis with Spectre. The output square noise power after the CDS of the first stage amplifier is shown in Fig. 8.
Figure 8. Simulated output square noise power
Rooting the integration the square noise power from 1Hz
TABLE I. SUMMARY OF ACCELEROMETER SPECIFICATIONS
System specifications
Resonant frequency 4.98kHz Mechanical noise 20.65μg/√Hz
Area (without/with rigid frame) 600um×470um / 700um×570um Circuit specifications
DC gain 44dB
Input-referrd noise 9.82 nV/√Hz Power 36uW
VI. CONCLUTIONS
The proposed circuit provides an effective solution to micropower low noise CMOS readout circuit. The CS and CDS technique is realized to reduce the offset voltage and flicker noise. The simulation results show the input-referred noise is 9.82nV/√Hz for 100Hz bandwidth and the power dissipation is 36uW. The circuit is useful due to the low noise and low power consumption. The MEMS/IC co-design flow of CMOS MEMS accelerometers provides effective system evaluation for monolithic CMOS MEMS accelerometer with readout circuit design.
ACKNOWLEDGMENT
The authors would like to acknowledge fabrication support provided by National Chip Implementation Center (CIC) and National Center of High-performance Computing for computer time and facilities. This work was conducted by Trans.-Wireless Technology Laboratory (TWT Lab.), Hsin-chu, Taiwan and sponsored by the National Science Council, Taiwan under the contract: NSC99-2220-E-009-042.
REFERENCES
[1] B. V. Amini,R. Abdolvand, and F. Ayazi, "A 4.5-mW closed-loop Delta Sigma micro-gravity CMOS SOI accelerometer," Ieee Journal of Solid-State Circuits, vol. 41, pp. 2983-2991, Dec 2006.
[2] J. F. Wu,G. K. Fedder, and L. R. Garley, "A low-noise low-offset capacitive sensing amplifier for a 50-mu g/root Hz monolithic CMOS MEMS accelerometer," Ieee Journal of Solid-State Circuits, vol. 39, pp. 722-730, May 2004.
[3] H. W. Qu, D.Y. Fong, and H. K. Xie, "A Monolithic CMOS-MEMS 3-Axis Accelerometer With a Low-Noise, Low-Power Dual-Chopper Amplifier," Ieee Sensors Journal, vol. 8, pp. 1511-1518, Sep-Oct 2008.
[4] M. Paavola, et al., "A micropower interface ASIC for a capacitive 3-axis micro-accelerometer," Ieee Journal of Solid-State Circuits, vol. 42, pp. 2651-2665, Dec 2007.
[5] M. Paavola, et al., "A Micropower Delta Sigma-Based Interface ASIC for a Capacitive 3-Axis Micro-Accelerometer," Ieee Journal of Solid-State Circuits, vol. 44, pp. 3193-3210, Nov 2009.
國科會補助專題研究計畫項下出席國際學術會議心得報告
NSC 99-2220-E-009 -042- 會議
名稱
(中文) 2011 年 IEEE 國際電路與系統研討會
(英文) 2011 IEEE International Symposium on Circuits and Systems 發表
論文 題目
(中文)單晶片含截波相關雙重取樣讀出電路之互補金氧半導體微電子機械系統 加速度計
(英文) A Monolithic CMOS MEMS Accelerometer with Chopper Correlated Double Sampling Readout Circuit
一、參加會議經過
今年 (2011) 的 IEEE 國際電路與系統研討會議 (IEEE International Symposium on Circuits and Systems) 在巴西里約熱內盧舉行。IEEE International Symposium on Circuits and Systems 多年來為推動電路與系統技術的重要國際研討會。今年會議全程 四天，論 (Paper#1439 “A Monolithic CMOS MEMS Accelerometer with Chopper Correlated Double Sampling Readout Circuit”為口頭演說論文，聽眾反應相當良好，並清楚的回答了三個問 題。
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