Chapter 2 Performance of DTMOS with Polysilicon and Metal Gates under
2.1.2 Motivation
According to above, high-K/ metal gate arranging in pairs DT-operation at low temperature may obtain very excellent current gain, especially when the applied gate bias surpasses the ZTC point bias. We will compare the fit and unfit quality of polysilicon and metal gates, and simultaneously discuss those advantages and disadvantages of normal and DT modes to figure out the trade-off.
7 2.2 Experiment
2.2.1Device fabrication
All transistors used in this work were fabricated by state-of-the-art 300 mm wafer foundry technology. HfSiO with Hf/(Hf+Si) ratio of 50% was annealing under . The high-K and 100 metal films were deposited by atomic-layer deposition (ALD) with 40 cycles and physical vapor deposition (PVD) techniques, respectively, followed by a 1000 polysilicon cap layer. In addition, before deposited the high-K dielectric, the chemical oxide was used as the interfacial layer. After gate patterning, halo implantation was used to optimize the short channel control. Eventually, a high-temperature annealing during source/drain activation and BEOL followed.
2.2.2Measurement setup
First, we set three operation modes, namely DT-A mode ( ), DT-B mode ( ), and normal mode ( ). Here, the threshold voltage is defined by constant current method [ = 40( ) nA] which painstakingly makes drain current independent of device geometry, and the measurement is simple with only one voltage measurement necessary.
In addition, the definition of drain induced barrier lowing (DIBL) and subthreshold swing (SS) are as following:
(def. 2-1) and
(def. 2-2)
8
We would extract DIBL and subthreshold swing from curves measured by Keithley 4200 semiconductor parameter analyzer over wide operation temperature ranges from 223K to 398K.
Finally, CV characteristics are measured at a frequency of 1MHz with different metal gate devices to extract the equivalent oxide thicknesses and discuss the gate control capability.
2.3 Results and Discussions
2.3.1 The Comparison of Performance for DTMOS with Polysilicon and Metal Gates under Different Body Bias Effects
2.3.1.1 Characteristics of Drain Current
Fig. 2-1 shows the characteristics of with polysilicon, TaC, and TiN gates under DT-mode, respectively. In DT-mode with connecting gate to bulk together, due to the threshold voltage is a function of , the higher would reduce the body charge and thus the threshold voltage.
The reduction of body charge would lead to a lower effective normal field in the device and bring on the higher carrier mobility. The normal field could be expressed as following:
(eq. 2-3)
In addition, the net result of threshold voltage reduction is effective to increase the inversion charge or equivalently the gate capacitance as shown in eq. 2-4, and provide an effectively thinner gate oxide for DTMOS [5].
9
(eq. 2-4)
The improvements of mobility and inversion charge lead to a higher current drive in DTMOS, especially under DT-B mode which has the highest body bias while is fixed. Moreover, low temperature operation and metal gate actually further enhance the performance [19].
However, we have forbidden that , so, although higher value of brings about higher reduction of threshold voltage and higher drain current gain, but it also reduces the upper bound of and thus the corresponding on-state drain current.
2.3.1.2 Characteristics of Threshold Voltage
The theoretical threshold voltage for large-geometry, n-channel device on uniformly doped substrates with body bias is expressed as [20]:
(eq. 2-5)
is the working function difference between the gate material and the bulk
semiconductor; is the flat band voltage; is the potential difference between the Fermi level and the intrinsic Fermi level of the bulk semiconductor; is the gate oxide capacitance; is the fixed oxide charge, and is the channel doping concentration.
Here, supposing , , and of the three devices are the same, for a low threshold voltage, it’s preferable to have low , high , and high . As shown
10
in Table 2.1 [2][3][21] and Fig. 2-2, actually induces the profoundest influence on threshold voltage. So, even though polysilicon gate device shows the lowest in Fig. 2-3 due to poly-depletion capacitance [22], still has the lowest threshold voltage among the three devices. Similar results for PMOS are shown in Fig. 2-4 and 2-5.
Before discussing roll-off, we need to know how the gate influences the formation of inversion layer under DT-mode. In subthreshold region, would lower the potential barrier height of the source node [23]:
(eq. 2-6)
is the intrinsic potential of source node. In the thermal equilibrium ( :
(eq. 2-7)
is the surface potential, and is the intrinsic potential of p- junction for p type substrate and type source region.
On other hand, the influences of body bias on surface potential is negligible due to no inversion charge, so can be consider as a function of only normal bias [20][23].
In addition, the lowing of induced by could promote the formation of inversion layer, so we define the gate control capability of DTMOS in subthreshold region as following:
(def. 2-3)
We know that applying to the substrate is equivalent to dropping the voltages of all other node of the device, namely, gate, drain, and source, by . So, now the
11
normal bias equals [23], and we have the following relationship:
(eq. 2-8)
Differentiating eq.2-8 with respect to yields:
(eq. 2-9)
is the capacitance of depletion layer. The relative change of and is calculated as:
(eq. 2-10)
On the other hand, the relative change of and is calculated as following:
(eq. 2-11)
So, def. 2-3 is calculated as:
(eq. 2-12)
According to eq. 2-7, while equals , a large amount of electrons inject to the surface from source node, and then inversion layer is formed.
Now would influences not only but also due to the injection of inversion charge. Finally the surface potential begins to couple with the body bias.
12
From mathematics viewpoint, according to eq. 2-12, lower
and higher could increase the result value. Furthermore, we use body effect parameter as following to figure out the gate control capability:
(def. 2-4)
As shown in Fig. 2-6, metal gates would have better gate control capability, especially at low temperature, and thus improve the roll-off as in Fig. 2-7.
Ideally, if equals 1, no matters how
changes, the gate control capability would not be effected and always equals 1, but in reality, there are some non-ideal factors existing, such as substrate parasitic resistance [7], so the gate control capability under DT-B mode don’t equal 1, and it changes from device to device. For all this, the roll-off under DT-B mode is still improved much better than the other two modes as usual.
2.3.1.3 Characteristics of Drain Induced Barrier Lowing (DIBL)
Source and drain depletion regions are a certain fraction of the channel. When the effective channel length is shorter, the drain is closer to the source, and can influence , so that the channel carrier concentration at that location is no longer fixed, and short channel effect (SCE) starts to occur. The lowing of causes an injection of extra carriers, thereby increasing the currents in both on-state and subthreshold regimes, so, short would enhance DIBL effect as shown in Fig.
2-8 and 2-9, and also result in higher subthreshold swing as shown in next section [20]. Under DT-mode, due to the narrower S/D depletion width induced by forward body bias, DT-B mode shows the lowest DIBL [7]. In addition, the two metal gates
13
exhibit their inherent stronger gate control capability once more as shown in Fig.
2-10.
Being worth mentioning, the DIBL effect is defined as the vertical parallel shift of curve at a given drain voltage and elevated drain voltage in the subthreshold regime [24]. For PMOS counterparts, long-channel behavior is totally lost while scaling down to 0.1 , and the curves are no longer vertical parallel; as a result, the gate length small than 0.1 is not discussed here.
2.3.1.4 Characteristics of Subthreshold Swing
When , the corresponding drain current is called the subthreshold current.
In weak inversion and depletion, the electron charge is small and the drain current is dominated by diffusion. According to def. 2-3, we can deduce that subthreshold current for DTMOS could be as following [23]:
(eq. 2-13)
According to def. 2-2, subthreshold swing of DTMOS can now be calculated as:
(eq. 2-14)
According to ex-part about DIBL, we’ve known that SCE would induce higher subthreshold swing as in Fig. 2-11 and 2-12. Furthermore, as in Fig. 2-13, metal gate devices under DT-B mode unfold the better performance again due to their excellent gate control capability.
As well as DIBL, while down to sub-0.1 the subthreshold swing for PMOS counterparts become too worst to be extracted; massive increasing of above-threshold and subthreshold currents cause those devices not turned off any more.
14
2.3.2 Comparison of Performance for DTMOS under Different Operation Temperatures
In the section, by comparing the experimental data with theoretical concepts, we present a study of the temperature dependence on the electric characteristics for DTMOS.
From the basic equations as shown as following [25]:
(eq. 2-15) and
(eq. 2-16) is the energy gap at T= 0K, we abtain:
(eq. 2-17) and
(eq. 2-18)
According to def. 2-4 and eq. 2-17, we know that:
(eq. 2-19)
In terms of eq. 2-18 and 2-19, elevated temperature results in threshold voltage reduction and degradation of gate control capability as shown in Fig. 2-6 [24][26-27].
Hence high temperature deteriorates SCE, such as roll-off, DIBL, and subthreshold swing shown as from Fig. 2.-14 to Fig. 2-37.
In addition, in order to derive the detailed temperature dependence of subthreshold
swing, we start from eq. 2-14 where the terms and
both increase with
15
temperature while , so the subthershold swing of DTMOS would be more sensitive in temperature.
2.3.3 Existence of ZTC point for DTMOS
According Fig. 2-38, we infer that there is a way to obtain low leakage and high on-state current at the same time: If the ZTC point for DTMOS exists, we could apply
higher than , the ZTC bias, under low temperature operation to obtain the excellent current gain.
From Fig. 2-39, regardless of normal or DT modes, a remarkable staggered spot appears, that’s a strong evidence of the existence of ZTC point. By far, the phenomenon is more obvious in Fig. 2-40. At , the drain current at high temperature is high due to ; at , since the ZTC point appears, the curves collaborate with each other; At , high temperature results in low on-state current, and then we can deduce that
. After proving the existence of ZTC point, now we are going to deliberate the theoretical model of ZTC point for DTMOS in next chapter to help us achieve the excellent current gain.
2.4 Summary
In the session, we define the gate control capability for DTMOS. From the theoretical inference process, we find that higher and lower can result in higher gate control capability; on the other hand, from the experimental results, metal gates have lower than polysilicon gate, and low temperature operation further reduces , so metal gate devices under DT-B mode at low temperature operation bring about best gate control capability, along with excellent performance, such as
16
improved roll-off, better DIBL, and lower subthreshold swing.
In the end of the chapter, we show the existence of ZTC point for DTMOS, which could tell us how to hypothesize the supply voltage to get the best current gain under low temperature operation.
17 (a)
(b)
(C)
Fig. 2-1 Drain current versus gate voltage for NMOS with (a) polysilicon (b) TaC (c) TiN gate under normal, DT-A and DT-B modes. The operation temperature is fixed at 223K.
18
Table 2.1 Effective work function lists.
Poly-Si TaC TiN
NMOS_EWF (eV) 4.1 4.45 4.7
PMOS_EWF (eV) 5.2 4.45 4.7
19 (a)
(b)
(C)
Fig. 2-2 Threshold voltage versus gate length for NMOS with (a) polysilicon (b) TaC (c) TiN gate under normal, DT-A and DT-B modes. The operation temperature is
20 (a)
(b)
(C)
Fig. 2-3 High frequency C-V characteristics at 1 MHz for NMOS with (a) polysilicon (b) TaC (c) TiN gate.
-1.2 -0.6 0.0 0.6 1.2 1
2 3 4
Cor.=2.01nm L=10m,W=10m
@ Temp = 25oC
TiN Gate
NMOS
Capacitance (pf)
Gate Voltage (V)
-1.2 -0.6 0.0 0.6 1.2 1
2 3 4
L=10m,W=10m
@ Temp = 25oC Poly Gate
NMOS
Capacitance (pf)
Gate Voltage (V)
Cor.=2.27nm
-1.2 -0.6 0.0 0.6 1.2 1
2 3 4
Cor.=1.75nm
L=10m,W=10m
@ Temp = 25oC
TaC Gate
NMOS
Capacitance (pf)
Gate Voltage (V)
21 (a)
(b)
(C)
Fig. 2-4 Threshold voltage versus gate length for PMOS with (a) polysilicon (b) TaC (c) TiN gate under normal, DT-A and DT-B modes. The operation temperature is
22 (a)
(b)
(C)
Fig. 2-5 High frequency C-V characteristics at 1 MHz for PMOS with (a) polysilicon (b) TaC (c) TiN gate.
-1.2 -0.6 0.0 0.6 1.2 2
3 4
5 L=10m,W=10m
@ Temp = 25oC
TiN Gate
PMOS
Capacitance (pf)
Gate Voltage (V)
Cor.=2.28nm
-1.2 -0.6 0.0 0.6 1.2 2
3 4 5
Cor.=2.28nm L=10m,W=10m
@ Temp = 25oC
Poly Gate
PMOS
Capacitance (pf)
Gate Voltage (V)
-1.2 -0.6 0.0 0.6 1.2 2
3 4 5
Cor.=1.77nm
L=10m,W=10m
@ Temp = 25oC
TaC Gate
PMOS
Capacitance (pf)
Gate Voltage (V)
23 (a)
(b)
Fig. 2-6 of polysilicon, TaC, and TiN gates over a range of operation temperature from 298K to 398K for (a) NMOS (b) PMOS.
0.00 0.05 0.10 0.15 0.20 0.25
NMOS
TaC TiN Poly
Vsb)
298K 318K 338K 358K 378K 398K
0.00 0.05 0.10 0.15 0.20 0.25
Vsb)
PMOS
TaC TiN Poly
298K 318K 338K 358K 378K 398K
24 (a)
(b)
Fig. 2-7 Threshold voltage roll-off characteristics of (a) NMOS (b) PMOS with polysilicon, TaC and TiN gate under normal, DT-A and DT-B modes, respectively.
The operation temperature is fixed at 223K.
0.00 0.05 0.10 0.15 0.20 0.25 0.30
Vt=Vt(L=1m)-Vt(L=0.055m)
Vt/Vt(L=1m) NMOS@ W=10m@ Temp = -50oC
Normal mode DT-A mode DT-B mode
Poly TaC TiN
0.00 0.05 0.10 0.15 0.20 0.25
0.30 Vt=Vt(L=1m)-Vt(L=0.1m)
Vt/Vt(L=1m)
PMOS@ W=10m@ Temp = -50oC
Normal mode DT-A mode DT-B mode
Poly TaC TiN
25 (a)
(b)
(C)
Fig. 2-8 DIBL versus gate length for NMOS with (a) polysilicon (b) TaC (c) TiN gate under normal, DT-A and DT-B modes. The operation temperature is fixed at 223K.
0.0 0.2 0.4 0.6 0.8 1.0
26 (a)
(b)
(C)
Fig. 2-9 DIBL versus gate length for PMOS with (a) polysilicon (b) TaC (c) TiN gate under normal, DT-A and DT-B modes. The operation temperature is fixed at 223K.
0.0 0.2 0.4 0.6 0.8 1.0
27 (a)
(b)
Fig. 2-10 DIBL of (a) NMOS (b) PMOS with polysilicon, TaC and TiN gate under normal, DT-A and DT-B modes, respectively. The operation temperature is fixed at 223K.
0 10 20 30 40 50 60 70 80
DIBL (mV/V)
NMOS
@ W=10m, L=0.1m
@ Temp = -50oC
Normal mode DT-A mode DT-B mode
Poly TaC TiN
0 10 20 30 40 50 60 70 80
DIBL (mV/V)
PMOS
@ W=10m, L=0.24m
@ Temp = -50oC
Normal mode DT-A mode DT-B mode
Poly TaC TiN
28 (a)
(b)
(C)
Fig. 2-11 Subthershold swing versus gate length for NMOS with (a) polysilicon (b) TaC (c) TiN gate under normal, DT-A and DT-B modes. The operation temperature is fixed at 223K.
29 (a)
(b)
(C)
Fig. 2-12 Subthershold swing versus gate length for PMOS with (a) polysilicon (b) TaC (c) TiN gate under normal, DT-A and DT-B modes. The operation temperature is fixed at 223K.
30 (a)
(b)
Fig. 2-13 Subthershold swing of (a) NMOS (b) PMOS with polysilicon, TaC and TiN gate under normal, DT-A and DT-B modes, respectively. The operation temperature is fixed at 223K.
45 50 55 60 65 70 75 80
Swing (mV/dec)
NMOS
@ W=10m, L=0.1m
@ Temp = -50oC
Normal mode DT-A mode DT-A mode
Poly TaC TiN
45 50 55 60 65 70 75 80
Swing (mV/dec)
PMOS
@ W=10m, L=0.24m
@ Temp = -50oC
Normal mode DT-A mode DT-B mode
Poly TaC TiN
31 (a)
(b)
(C)
Fig. 2-14 Threshold voltage versus gate length for NMOS with polisilicon gate under (a) normal (b) DT-A (c) DT-B gate mode for different temperatures. The operation temperatures are fixed at 223K, 298K, 348K, and 398K, respectively.
0.0 0.2 0.4 0.6 0.8 1.0
32 temperatures are fixed at 223K, 298K, 348K, and 398K, respectively.
0.0 0.2 0.4 0.6 0.8 1.0
33 temperatures are fixed at 223K, 298K, 348K, and 398K, respectively.
0.0 0.2 0.4 0.6 0.8 1.0
34 (a)
(b)
(C)
Fig. 2-17 Threshold voltage roll-off for NMOS with (a) polysilicon (b) TaC (c) TiN gate under normal, DT-A, DT-B gate mode for different operation temperatures. The operation temperatures are fixed at 223K, 298K, 348K, and 398K, respectively.
0.00
35 (a)
(b)
(C)
Fig. 2-18 Threshold voltage versus gate length for PMOS with polisilicon gate under (a) normal (b) DT-A (c) DT-B gate mode for different temperatures. The operation temperatures are fixed at 223K, 298K, 348K, and 398K, respectively.
0.0 0.2 0.4 0.6 0.8 1.0
36 temperatures are fixed at 223K, 298K, 348K, and 398K, respectively
0.0 0.2 0.4 0.6 0.8 1.0
37 temperatures are fixed at 223K, 298K, 348K, and 398K, respectively.
0.0 0.2 0.4 0.6 0.8 1.0
38 (a)
(b)
(C)
Fig. 2-21 Threshold voltage roll-off for PMOS with (a) polysilicon (b) TaC (c) TiN gate under normal, DT-A, DT-B gate mode for different operation temperatures. The operation temperatures are fixed at 223K, 298K, 348K, and 398K, respectively.
0.0
39 (a)
(b)
(C)
Fig. 2-22 DIBL versus gate length for NMOS with polisilicon gate under (a) normal (b) DT-A (c) DT-B gate mode for different temperatures. The operation temperatures are fixed at 223K, 298K, 348K, and 398K, respectively.
0.0 0.2 0.4 0.6 0.8 1.0
40 (a)
(b)
(C)
Fig. 2-23 DIBL versus gate length for NMOS with TaC gate under (a) normal (b) DT-A (c) DT-B gate mode for different temperatures. The operation temperatures are fixed at 223K, 298K, 348K, and 398K, respectively.
0.0 0.2 0.4 0.6 0.8 1.0
41 (a)
(b)
(C)
Fig. 2-24 DIBL versus gate length for NMOS with TiN gate under (a) normal (b) DT-A (c) DT-B gate mode for different temperatures. The operation temperatures are fixed at 223K, 298K, 348K, and 398K, respectively.
42 temperatures are fixed at 223K, 298K, 348K, and 398K, respectively.
43 (a)
(b)
(C)
Fig. 2-26 DIBL versus gate length for PMOS with polisilicon gate under (a) normal (b) DT-A (c) DT-B gate mode for different temperatures. The operation temperatures are fixed at 223K, 298K, 348K, and 398K, respectively.
44 (a)
(b)
(C)
Fig. 2-27 DIBL versus gate length for PMOS with TaC gate under (a) normal (b) DT-A (c) DT-B gate mode for different temperatures. The operation temperatures are fixed at 223K, 298K, 348K, and 398K, respectively.
45 (a)
(b)
(C)
Fig. 2-28 DIBL versus gate length for PMOS with TiN gate under (a) normal (b) DT-A (c) DT-B gate mode for different temperatures. The operation temperatures are fixed at 223K, 298K, 348K, and 398K, respectively.
0.0 0.2 0.4 0.6 0.8 1.0
46 temperatures are fixed at 223K, 298K, 348K, and 398K, respectively.
0
47 operation temperatures are fixed at 223K, 298K, 348K, and 398K, respectively.
48 (a)
(b)
(C)
Fig. 2-31 Subthershold swing versus gate length for NMOS with TaC gate under (a) normal (b) DT-A (c) DT-B gate mode for different temperatures. The operation temperatures are fixed at 223K, 298K, 348K, and 398K, respectively.
49 (a)
(b)
(C)
Fig. 2-32 Subthershold swing versus gate length for NMOS with TiN gate under (a) normal (b) DT-A (c) DT-B gate mode for different temperatures. The operation temperatures are fixed at 223K, 298K, 348K, and 398K, respectively.
0.0 0.2 0.4 0.6 0.8 1.0
50 operation temperatures are fixed at 223K, 298K, 348K, and 398K, respectively.
51 operation temperatures are fixed at 223K, 298K, 348K, and 398K, respectively.
52 temperatures are fixed at 223K, 298K, 348K, and 398K, respectively.
0.0 0.2 0.4 0.6 0.8 1.0
53 temperatures are fixed at 223K, 298K, 348K, and 398K, respectively.
0.0 0.2 0.4 0.6 0.8 1.0
54 operation temperatures are fixed at 223K, 298K, 348K, and 398K, respectively.
55 (a)
(b)
Fig. 2-38 Ion-Ioff characteristics of TiN gate NMOS at (a) 223K (b) 298K.
10-7 10-6 10-5 10-4 10-3 10-2 10-1 10-15
10-14 10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6
@ Temp = -50oC TiN Gate
Ioff (A/m)
Ion (A/m)
Normal-A mode DT-A mode Normal-B mode DT-B mode
10-7 10-6 10-5 10-4 10-3 10-2 10-1 10-15
10-14 10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6
@ Temp = 25oC TiN Gate
Ioff (A/m)
Ion (A/m)
Normal-A mode DT-A mode Normal-B mode DT-B mode
56 (c)
(d)
Fig. 2-38 Ion-Ioff characteristics of TiN gate NMOS at (c) 348K (d) 398K.
10-7 10-6 10-5 10-4 10-3 10-2 10-1 10-15
10-14 10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6
@ Temp = 75oC TiN Gate
Ioff (A/m)
Ion (A/m)
Normal-A mode DT-A mode Normal-B mode DT-B mode
10-7 10-6 10-5 10-4 10-3 10-2 10-1 10-15
10-14 10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6
@ Temp = 125oC TiN Gate
Ioff (A/m)
Ion (A/m)
Normal-A mode DT-A mode Normal-B mode DT-B mode
57 (a)
(b)
Fig. 2-39 Drain current versus gate voltage for TiN gate NMOS with different gate bias and different operation temperatures under (a) normal (b) DT-C mode. The sweep range of gate bias is from 0.8V to 1.4V, and the operation temperatures are fixed 298K, 348K, and 398K, respectively.
0.0 0.4 0.8 1.2 1.6 0.000
0.002 0.004 0.006 0.008
TiN Gate
L=0.055m,W=10m
Drain current (A)
Gate voltage (V)
25oC 75oC 125oC
@Vd=0.7V Normal mode
0.0 0.4 0.8 1.2 1.6 0.000
0.002 0.004 0.006 0.008
TiN Gate
L=0.055m,W=10m
Drain current (A)
Gate voltage (V)
25oC 75oC 125oC
@Vd=0.7V DT-C mode
58 (a)
(b)
Fig. 2-40 Drain current versus drain voltage for TiN gate NMOS with different gate bias and different operation temperatures under (a) normal (b) DT-C mode. The sweep range of gate bias is from 0.8V to 1.4V, and the operation temperatures are fixed 298K, 348K, and 398K, respectively.
0.00 0.25 0.50 0.75 1.00 0.0
5.0x10-3 1.0x10-2
125oC:Cross 75oC:Hollow 25oC:Solid
TiN Gate L=0.055m,W=10m
Drain current (A)
Drain voltage (V)
Vg=0.8V Vg=1.1V Vg=1.4V
@Vd=0.7V DT-C mode
0.00 0.25 0.50 0.75 1.00 0.0
5.0x10-3 1.0x10-2
125oC:Cross 75oC:Hollow 25oC:Solid
TiN Gate L=0.055m,W=10m
Drain current (A)
Drain voltage (V)
Vg=0.8V Vg=1.1V Vg=1.4V
@Vd=0.7V Normal mode
59 Chapter 3
The Compact Modeling of ZTC Point for DTMOS
3.1 Introduction
3.1.1 Backgrounds
According to the general backgrounds, recently there has been a growing interest in designing circuits that operate reliably over a widespread temperature range. It is desirable to drive circuits designed for high temperature applications at ZTC point where the drain current shows insensitive to the temperature.
The most main origin of ZTC point is because of mutual compensation of the dependences of mobility and threshold voltage on temperature in FETs. Exactly said, carrier mobility and threshold voltage both drop along with the temperature rise, and that results in the existence of ZTC point in MOS transconductance characteristics [28]. Many literatures had already confirmed the existence of ZTC point by the empirical datum, and developed the ZTC point theory from simple drain current model. With increasing the consideration factors, the error between the empirical datum and the theoretical value would reduce.
While at ZTC point, the drain current would not change along with temperature;
therefore, the necessary condition of the existence of ZTC point is shown as following:
(eq. 3-1)
We can obtain the corresponding gate bias, , from eq. 3-1. When
, those parameters related to temperature appearing in the drain
60
current theoretical formula must compensate mutually with each other, causing this dependence of on temperature to offset, and that’s just the sufficient condition of the existence of ZTC point [10].
In addition, the optimal is obtained by the least squares method which is minimizing the difference between the left- and the right-hand sides of the necessary condition (eq. 3-1) over a specified operating temperature range [ , ] [10-15].
At first, for the bulk MOSFET, the drain current model is in direct proportion to
At first, for the bulk MOSFET, the drain current model is in direct proportion to