2.4 Architectures of Sigma-Delta Modulator
2.4.6 Multi-bit Quantizer Sigma-Delta Modulator
The demands of high resolution and high bandwidth ADC are more and more in recent years. In a high signal bandwidth, OSR of ΣΔ ADC can’t be too high, and the peak SNR of a modulator with such limited OSR can’t satisfy of high resolution applications, if we use higher order architecture, then the performance will degrade due to instability. So the most general method to increase performance is to use
ΣΔ
distance between quantizer level VLSB in (2.4) is much smaller due to increasing of B, and according to (2.3), the power of quantization noise is attenuated. Fig. 2.17 is the results of theoretical peak SNR of ΣΔ modulator versus oversampling ratio, with different order and quantizer bits, it is noted that peak SNR of the same OSR is increase 6 dB with each additional bit number in quantizer, and at low OSR, low order higher bit number architecture has equivalent performance as high order architecture.
This result is usable for high bandwidth applications, and the power consumption of digital circuit in ΣΔ modulator is reduced due to lower sampling rate [41].
160
0 50 100 150 200 250 300
20 40 60 80 100 120 140
O2B1 O2B2 O2B3 O3B1
OSR
SNR
Fig. 2.17 SNR vs. OSR with different quantizer bit number
Because of using multi-bit quantizer, so we also need to use multi-bit DAC(Digital-to Analog Converter) to transfer the digital output to analog signal, and feed it back to integrator. The most significant disadvantage is the non-linearities introduced by multi-bit DAC can degrade the performance of ΣΔ converter, like Fig. 2.18. It is a linear model of multi-bit modulator, where E(Q) and E(D) represent the quantization noise and feedback DAC noise respectively. The values of these capacitor elements in DAC will not equal to ideal values that we need, it is due to
ΣΔ
process variation, typical value of mismatch in modern CMOS technology is about 0.05% ~ 0.5%. In recent years, so many researches are make efforts on reduce DAC noise due to mismatch, such as trimming [42], Dynamic element matching(DEM)[33, 43], although trimming is effective, but it has a expensive production step. So, DEM becomes more and more popular because of its efficiency and cheaper cost.
Fig. 2.18 Multi-bit architecture
2.4.7 Multi-bit Sigma-Delta Modulator use DEM Technique
Dynamic element matching is a different approach to decrease the DAC noise, it is used to improve the linearity of pure DACs [44], but now it is most used in inner DAC of multi-bit ΣΔ modulator. A DAC with DEM technique is illustrated in Fig.
2.19, bits thermometer code is put into the element selection logic block, and the function of element selection logic is try to select DAC elements in such way let the errors introduced by DAC average to zero for several operation periods. Because the DEM block is located in feedback loop, so its delay must be very small prevent to degrade the performance of converter, therefore the algorithm used in the DEM block must be simple. There are several techniques of DEM, such as Randomization
2B
ΣΔ
[45], Clocked Averaging (CLA) [47], Individual Level Averaging (ILA) [46], Data Weighted Averaging (DWA) [47], Randomization is the first approach to use DEM technique in ADC, and DWA offers a good performance to reduce DAC error, in this section, an overview introduction of these two algorithms will be presented, and the operation principle of them will be explained.
ΣΔ
1 2B−
1 2 2B
2B
Fig. 2.19 A B-bit DAC with DEM technique
2.4.8 Decimator
In A/D converter, digital decimator is used to process digital signal of the quantizer output, the high speed data word after oversampling modulation can’t be used directly. Because there have original signal and quantization noise among it, so the main function of decimator is to convert the oversampled B-bit output words of the quantizer at a sampling rate of fs to N-bit words at Nyquist rate of input, and removes the noise out of signal band. In order to prevent the noise introduced by other frequency, the decimator filter must have very flat signal pass-band, and sharp transition region and enough signal attenuation in stop band. Two-stage decimator is used in a general situation, because that single stage decimator is difficult to convert sampling rate to Nyquist rate in 1 time and without degrading SNR. In the first stage, we can down-sample the sample frequency to 2~4 times of Nyquist frequency, and in the second stage, we can use IIR or FIR filter that have high linearity [42]. For a large
ΣΔ
OSR, multi-stage decimator is used.
2.4.9 Performance Metrics for a ΣΔ Modulator
In order to understand the performance merits used to specify the behavior of modulator, several specifications concerning the performance are discussed [30].
ΣΔ
․Signal to Noise Ratio: The SNR of a data converter is the ratio of the signal power to the noise power, measured at the output of the converter for a certain input amplitude. The maximum SNR that a converter can achieve is called the peak SNR.
․Signal to Noise and Distortion Ratio: The SNDR of a converter is the ratio of the signal power to the power of the noise and the distortion components, measured at the output of the converter for a certain input amplitude. The maximum SNDR that a converter can achieve is called the peak SNDR.
․Dynamic Range at the input: The DRi is the ratio between the power of the largest input signal that can be applied without significantly degrading the performance of the converter, and the power of the smallest detectable input signal.
The level of significantly degrading the performance is defined as the point where the SNDR is 6 dB bellow the peak SNDR. The smallest detectable input signal is determined by the noise floor of the converter.
․Dynamic Range at the output: The dynamic range can also be considered at the output of the converter. The ratio between maximum and minimum output power is the dynamic range at the output DRo, which is exactly equal to peak SNR.
․Effective Number of Bits: ENOB gives an indication of how many bits would be required in an ideal quantizer to get the same performance as the converter. This numbers also includes the distortion components and can be calculated from (2.6)
02 . 6
76 . ENOB= SNR−1
(2.38)
․Overload Level: OL is defined as the relative input amplitude where the SNDR is decreased by 6dB compared to peak SNDR
Typically, these specifications are reported using plots like Fig. 2.17. This figure shows the SNR and SNDR of the ΣΔ converter versus the amplitude of the sinusoidal wave applied to the input of the converter. For small input levels, the distortion components are submerged in the noise floor of the converter. Consequently, the SNDR and SNR curves coincide for small input levels. When the input level increases, the distortion components start to degrade the modulator performance.
Therefore, the SNDR will be smaller than the SNR for large input signals. Note that these specifications are dependent on the frequency of the input signal and the clock frequency of the converter. Fig. 2.20 also shows that SNDR curves drop very fast once the overload point is achieved. This is due to the overloading effect of the quantizer which results in instabilities.
Fig. 2.20 Performance characteristic of a ΣΔ converter
3.OTA Non-Linear Gain Curve
Existing OTA nonlinear gain distortion models in Sigma-Delta Modulator consume much time to obtain. Usually OTA nonlinear gain curve parameters are identified directly from transistor-level designs. Although the nonlinear gain curve parameters obtained this way are more accurate, it is hard to generalize from one design case to another. In addition, there are two more problems. First, due to that they consume much time to obtain OTA nonlinear gain curve parameters, it is not practical to achieve desired results in a recursive way. Second, it is hard to know how nonlinear gain curve parameters are affected by sigma-delta modulator circuit
parameters, e.g., OTA dc gain Ao, OTA output swing voltage VOS, etc.
Two of major op-amp architectures are popular with low-power IC design. First architecture is the two-stage op amp. It consists of a cascade of V→I and I→V stages.
This two-stage op amp is so widely used that we call it the classical two-stage op amp.
Second architecture major architecture is commonly called the folded-cascade op amp.
Architecture of classical two-stage architecture is widely used in SDM design. It comprises differential amplifier in first voltage stage and output amplifiers in second voltage stage, see as Fig. 3.1.
Fig 3.1 Two-Stage OTA architecture
By general application in sigma-delta modulator, our non-linear gain model built
of classical two-stage op-amp with class-A stage. It’s typical op-amp’s configuration schematic see as Fig.3.2.
In the practical op amp circuit, the nonlinearity of the gain is manifested by its dependency on amplifier output voltage . Fig. 3.3 shows a typical relationship between DC gain and , in which the maximum DC gain appears at
VO
VO AO
Fig. 3.2. A typical op-amp’s configuration schematic considering nonlinear DC gain
Fig. 3.3. A typical relationship between DC gain and Vo
center of scale and decreases as the magnitude of output voltage increases. This nonlinear gain introduces distortion in the sigma-delta modulator output spectrum.
After some HSPICE simulation based on TSMC 0.18μm, the results reveal that VGSQ of the output-stage transistors and the maximum DC-gain AO also affect the shape of
A0=570,VOS=1V
A0=321,VOS =1V
Fig.3.4. Two nonlinear gain curves with identical VOS but different A0
A0=331,VOS=1.6V
A0=321,VOS =1V
Fig.3.5. Two nonlinear gain curves with similar but different A0 VOS
the nonlinear curves. In order to make designers easier to use, it is must to replace
VGSQ by a more general parameter in circuit. By the basal op amp circuit concept, we can know the range of maximum output swing ( )VOS and VGSQ are germane relation with each other. Thus, in dealing with OTA distortions, we are basically faced with a family of nonlinearities.
About the distortion due to a particular nonlinear curve approximated by the polynomial:
) 1
( )
( o = 0 + 1 o+ 2 o2+ 3 o3+ 4 o4+L
VV A qV qV qV qV
A (3.1)
Because the nonlinear curve is even function, it can be simplified by:
) 1
( )
( o = 0 + 2 o2+ 4 o4+ 6o6+L
VV A qV qV qV
A (3.2)
Where is finite DC gain of OTA, and is the maximum finite DC gain when is in the neighborhood of 0V.
) (VO Av
VO
AO
Although some expressions for harmonic distortions are derived in [30] and [48], these results are not completed. They just offer an incomplete model, due to they model must use transistor level to assist their distortion model complete. In this subsection, we will drive a complete OTA gain distortion model for 0.18μm process.
There are two steps. In the first step, we try to model the family of nonlinear curves.
Next, based on this nonlinear curve model, we derive the distortion model. The behavior simulation model offered by [49] is applied to verify this model.
For the first step, our HSPICE simulation based on TSMC 0.18μm process model reveals that, in addition to output voltage Vo, both the VGS of output stage transistors and the maximum DC gain can affect the shape of the nonlinear curves.
Thus, in dealing with OTA distortions, we are basically faced with a family of nonlinearities. Since VGSQ is inversely proportional to the range of maximum output swing , we identify , and V as the three parameters that can affect OTA DC gain . We simulated on a classical two-stage operation amplifier shown in Fig.
3.6 to produce two specific cases shown in Fig. 3.4 and Fig. 3.5. Figure 3.5 shows how variation in can affect the curve shape. Figure 3.5 demonstrate the case when
AO
OS
VOS
A
VO AO
V
AO
variation is mainly in . In order to model the nonlinear DC gain , we tried various combination of and to the curve shape. In order to model the nonlinear DC gain , we tried various combination of and to create a set of representative curves for the family of nonlinear DC gain curves. Then, after intensive
VOS
A
AV
O VOS
AV AO VOS
Fig. 3.6. A classical two-stage operation amplifier
trials and errors, we come up with the following function to fit the nonlinear curves.
( , , ) {1 0.5 [ (0.443 ) ( 0.443 1.2 ) 2]}
After performing Taylor’s series expansion on (14) over , the model we arrive at is of the form Because the q and q are the critical parameter for OTA gain distortion, we can
discriminate the circuit parameter effect upon OTA gain distortion clearly.
In the past, it is hard to decide DC gain to achieve high-linear. Because modern ICs are asked for low power consumption, DC gain isn’t the bigger the better.
Designers can plan a recursive way with our approach. For example, if designer expect the HD3 is -110 dB. Users can easily know that q2 is needed -0.170521 and q4 is needed -0.004846 and designers can decide important parameters (e.g., OTA dc gain, OTA output swing voltage etc) in design flow.
At last, we simulate a practical two op amps to verify our non-linear gain curve model. First, we simulate op-amp with class-B stage. It’s parameter is
Ao=68dB,Vos=±1.5V. See Fig.3.8, when Vo swing in (+0.87V~-0.87V), the simulation result of nonlinear curve function is close to the practical one. The 2nd order nonlinear coefficient of the nonlinear curve function q2= - 0.0593 is close to that of the practical case q2= -0.0561, but the 4th order nonlinear coefficient of the nonlinear curve function q4=-0.000586 is much larger than that of practical case q4=
-0.00873.
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2
1800 1900 2000 2100 2200 2300 2400 2500
Vo(V)
Differential Gain
Fig.3.8. Comparison between simulation of nonlinear curve function and practical design
Second, we simulate op-amp with class-A stage. It’s parameter is
Ao=50dB,Vos=±1.6V. See Fig.3.9, when Vo swing in (+1V~-1V), the simulation result of nonlinear curve function is close to the practical one. The 2nd order
nonlinear coefficient of the nonlinear curve function is close to that of the practical case , but the 4th order nonlinear coefficient of the nonlinear curve function is much larger than that of practical case since is very sensitive and difficult to be estimated, it causes that the 5th harmonic distortion estimation is not accurate,
1387 .
2=−0 q
q 1106
.
2=−0 q
0032 .
4=−0 4 4
q =−0.0451 q
Fig.3.9. Comparison between simulation of nonlinear curve function and practical design
Because our nonlinear gain model are build with class-A in second stage, The simulate with class-A is more accurate than class-B. No matter what Architecture is, q2 is still enough to obtain a accurate HD3. Because it’s the most important factor for HD3.
4. Distortion Due to the Non-Linear Gain of the Operational Amplifier
An ideal OTA with infinite gain doesn’t introduce any noise or distortion.
Practical OTAs not only have the characteristics of finite DC gain, but also the gain is nonlinear. In chapter four, we analyze the op amps non-linear gain phenomenon. We also obtain the non-linear gain curve model aimed the classical two-stage. So the next work is to obtain the expressions to estimate harmonic distortion introduced by integrator with our non-linear gain curve model.
(a) Sampling phase (b) integration phase Fig. 4.1. Switch-capacitor integrator with finite-gain amplifier
See Fig 4.1(a) and 4.1(b), First, in order to obtain more accurate distortion model we must analyze the charge transfer in integrator. By Fig. 4.1 we can obtain the charge transfer in integrator is
1 ( ) ( ) )
( − + ⋅ = O+− O− − a+− a−
I a S
S V V V V
V C V
C (4.1)
Arrange function
CI⋅(VO+−Va+)−CS⋅Va+=CI⋅(VO−−Va−)+CS⋅V (4.2)
Up to the present, we obtain three important functions in nonlinear gain analyze. First, the nonlinear gain curve model. Second, the charge transfer functions in integrator.
Third, the behaving characteristic functions of op amp. See below
( ) (1 2 4 4) (4.3)
Substituting (4.3) and (4.4) into (4.5), one obtains the following expression
] final expression can be derived as
− Using Taylor’s series expansion on over Ao
−
1
In order to build a mathematical expression related to input signal magnitude for estimating the distortion caused by nonlinear DC gain, and must be expressed as functions of . In single-loop second-order sigma-delta modulator, when a signal apply to modulator input and quantization noise is not considered, can be represented as
The output signal of the first integrator can be represented input signal See Fig. 4.2
As t = (n+1/2)T, in integration phase
)
We can clean find that output voltage and input voltage are integral relation.
Then we simplify function
⎟⎠
Then (4.10) (4.15) replace Vo and Vs into the nonlinear tern
)
⎪⎪
In (4.18)-(4.21) we can obtain the relationships between the each parameter and power of the harmonic distortions, which are listed in Table 4.1.
Table 4.1 the relationship between the each parameter and the harmonic distortions
CI↑ CS↑ Ain↑ A0↑ Vos↑ OSR↑
Distortion size
↓ ↑ ↑ ↓ ↓ ↑
5.Behaving Model Simulation Results
We use a calculable behaving model to verify our nonlinear gain distortion model.[49]
The z-domain transfer function of a delayed integrator of Sigma-Delta Modulator is Where g and α are the integrator gain and leakage.
For a Typical integrator, the precise transfer function is
I The nonlinear curve is
(1 2 3 3 ) (5.3)
Then substitute into g and α
⎜⎜⎝
By above function, we could build an op amp model in Simulink. See as Fig.5.1
Fig. 5.1 an nonlinear op-amp model in simulink
Then, we take op amp model into the complete sigma delta modulator. See as Fig.5.2
Fig. 5.2 Non-ideal second-order SDM
Now, we can use the non-ideal OTA behaving model in sigma delta modulator to simulate the OTA nonlinear gain distortion.
Table.5.1 Comparison of theoretic result and behavior simulation of Case A
See as Table.5.1, Table.5.2, Table.5.3, we can find our model simulation results are close to behaving model simulation results. At different op-amp specifications, HD3 in our model is always close to simulation results.
Table.5.2 Comparison of theoretic result and behavior simulation of Case B
Table.5.3 Comparison of theoretic result and behavior simulation of Case C
6.Transistor Level Simulation Results
The proposed model serves as a powerful tool for analyzing nonlinear gain distortion for sigma delta modulator. In order to assess the accuracy of the proposed methodology at circuit-level, the circuit of Fig. 6.1 has been realized using classical two-stage architecture in Spice.
Because the magnitude of transfer function of first op amp in sigma delta modulator is one, all of its noise wouldn’t loss in SDM output. So we can just use an op amp to simulate gain distortion.
Fig.6.1. two-stage Op-Amp
The specifications op the op amp are DC-gain=69dB,Vos=±1.43V, a1=1. Its FFT print See as Fig.6.2. Note that the even order harmonic distortions are ideally zero due to the symmetry of fully differential OTA. The total harmonic distortion (THD) is mainly determined by the third harmonic distortion (HD3). By Fig.6.2 HD3 and HD5 is -52.1dB and -72.9dB respective, our model simulation is that HD3 and HD5 is -47.0227dB and -63.0224dB respective. We can find that our HD3 is close to Spice simulation, it’s different about 5dB. But the q4 of our model isn’t accurate enough, our HD5 isn’t close to Spice simulation. It’s different about 10dB. But HD5 can be
neglect always in common sigma delta design, its effect on signal in SDM is unobvious. This simulation results are listed in Table 6.1.
Fig6.2. Simulation FFT Results with a1=1, DC-gain=60dB VOS=1.43V FB=200k Table.6.1 Comparison of theoretic result and spice simulation
Theoretic (dB) Spice Simulation (dB)
HD3 -47.0227 -52.1 HD5 -63.1224 -72.9
7. Conclusions and Future Works
In this paper, our approach model not only nonlinear gain curve but also nonlinear OTA gain distortion. Due to saving time for circuit-level simulation, designer can use this model to obtain the expectant specification with a recursive way. Although the HD5 is not accurate enough, it isn’t a major cause of performance attenuation.
In this paper, our approach model not only nonlinear gain curve but also nonlinear OTA gain distortion. Due to saving time for circuit-level simulation, designer can use this model to obtain the expectant specification with a recursive way. Although the HD5 is not accurate enough, it isn’t a major cause of performance attenuation.