Plasma Treatment
3.2.4 NBTI in HfO 2 /SiON Gate Stacks
It is well-known that for the SiO2-based gate dielectrics, high voltage stress on the gate electrode of MOSFETs could change flatband or threshold voltage, in particular at elevated temperatures. This phenomenon is called bias temperature instability (BTI). Most of BTI researches on the SiO2 dielectric are focused on the negative BTI, because of aggravated degradation compare with positive BTI. Even more, Kimizuka et al. revealed that as the gate oxide thickness is scaled down to the range of 3.5nm, NBTI could become the bottleneck limitation to the SiO2 scaling than NMOS HCI [34]. NBTI of pMOSFETs is an important reliability issue for both digital and analog applications. Despite the many works on NBTI in order to keep NBTI at bay, including better modeling and improved processes, the basic rootcause mechanism is still not fully understood. Ogawa et al. proposed a model based on their experimental results [35].
3 3
Si ≡SiH +p+ ⇔Si ≡ ∗ +Si H+ Reaction-limited (3.1)
3 3 i
Si ≡SiH ⇔Si ≡ ∗+ Si H Diffusion-limited (3.2)
3 3 i
O ≡SiH+ p+ ⇔O ≡ ∗ +Si H (3.3)
interface bulk
(H+,Hi) ⇔(H+,Hi) (3.4)
It can be seen that the model can be separated into reaction-limited and diffusion-limited processes. The reaction-limited is dependent on the number of holes near the interface available to interact with Si-H bonds. Once the reaction-limited processes are equilibrated, the diffusion-limited processes are dependent on the rate of diffusion of hydrogen away from the
interface.
Figs. 3-25 (a) and (b) show Id, Gm-Vg characteristics before and after Vgo=-1.5V stress at room temperature and 125°C, respectively. A parallel shift of Id-Vg curve can be seen, and indicates that less △Nit is generated. Gm degradation is also alleviated. For confirmation, the generated interface state densities versus stress time are shown in Fig. 3-26. We can recall that the fresh Nit value is on the order of 8x1011 /cm2, which means that the amount of △Nit is relatively small, compared to Nit. △Nit is shown to obey the power-law, and the index is 0.24, exactly the same value as that in the conventional SiO2, indicating that △Nit follows the reaction-diffusion model. Fig. 3-27 shows that △Vthc, increases with increasing temperature.
The Dependence of △Nit and △Ntot on stress time is shown in Fig. 3-28. △Ntot is larger than
△Nit by more than an order, indicating that the bulk traps in HfO2, rather than interface state density generation, is responsible for the transistor degradation.
After a gate overdrive stress of -2V for 1000 seconds at either room temperature or 125°C, the resultant Id, Gm-Vg are shown in Figs. 3-29 (a) and (b), respectively. We can see that Id depicts only a parallel shift after 1000 seconds stress, and Gm peak shows less than 5%
degradation at room temperature. Similar trend is observed for the high temperature case.
Subthreshold swing changes only slightly after stressing. As shown in Fig. 3-30, the generated interface state densities are degraded by the temperature stress as expected. According to the theory of NBTI, the threshold voltage shift (|△Vthc|) should keep increasing because of the increasing oxide traps. Unfortunately, it does not follow the predicted trend in our samples, as shown in Fig. 3-31. There are two possibilities: one is the increased electron trapping that compensates the hole trapping, and the other is the occurrence of recombination of the hole trapping. Fig. 3-32 clarifies the culprit of threshold voltage shift, whether it stems from the oxide traps or the interface states. At low temperature, △Ntot is about two orders larger than
△Nit, indicating that trapping in the HfO2 bulk can be a very critical issue. However, Id
degradation curve in Fig. 3-33 reveals that the recombination of hole trapping is the root
cause of Fig. 3-31, as Id degradation should be worsen if the amount of total traps increases.
The recombination occurrence can be explained by the rapidly increasing electron current as the temperature rises, while the hole current remains the same, as shown in Fig. 3-34.
By changing the stress voltage to Vgo=-2.5V, a parallel shift is still obtained, as shown in Fig. 3-35 (a), and the subthreshold swing shows a slight increase after stress at 125 . It is ℃ shown in Fig. 3-37 that trapping effect in high-k bulk is still an order larger than N△ it, indicating that reaction-reaction model may not be suitable for HfO2/SiON gate stacks, due to the preponderant bulk traps, compared to interface traps. As shown in Fig. 4-36, the index of power-law increases from 0.06 at low temperature to 0.15 at 125°C. This may be due to the fact that larger stress voltage causes the valence band of the Si substrate to shift closer to the hole trap, which is located at =1.17eV, as already mentioned in Chapter two, so holes become easier to jump and get trapped.
ΦB
Fig. 3-38 and Fig. 3-39 compare the control sample and the sample with N2O plasma treatment under Vgo=-2.5V 125 . The improvement can be achieved after post℃ -N2O plasma treatment, especially at high temperature.
In conclusion, N△ it follows the reaction-diffusion model with a power-law index of 0.25, because our IL is still SiON. In addition, bulk traps always dominate the degradation of HfO2/SiON, which means that trapping effect is larger than hydrogen species effect. Fig. 3-40 shows that under dynamic stress, the recovery of N△ it is observed, and shows no dependence on the relaxation voltage. Fig. 3-41 shows that the trapping charges can be de-trapped by the relaxation voltage.
3.3 Summaries
Several kinds of reliability testing have been performed, such as dynamic stress, investigation of bulk or IL breakdown, and NBTI. It is found that post-N2O plasma treatment
may not be beneficial because of the resulting higher electrons trapping under AC stress, even though it exhibits several advantages as discussed in Chapter two. Bias temperature instability shows that leakage current could affect the threshold voltage shift behavior. Our data also confirm that two different mechanisms exist in HfO2/SiONgate stacks, i.e., trapping and the NBTI. And the effect of trapping is larger than the reaction-diffusion effect.
Chapter 4 Conclusion
4.1 Conclusion
In the thesis, we performed the post-deposition N2O plasma nitridation to enrich the HfO2 film quality. Several important phenomena were observed and summarized as follows.
First of all, Improvements in the electrical characteristics of the p+-poly gate pMOSFETs with HfO2/SiON gate stacks using post-deposition N2O plasma treatment have been demonstrated in this work. We have found that improvements include many aspects, such as reduced leakage current, better subthreshold swing, enhanced normalized transconductance, and higher driving current. These were ascribed to the lower interface states and bulk traps as confirmed by various types of charge pumping measurements.
In the second part of the thesis, we have used carrier separation method to clarify the breakdown in HfO2 or IL. The behavior is different for samples with and without N2O plasma treatments.
Finally, we have studied the dynamic stress and NBTI. △Vth is mainly caused by the trapping in the HfO2, rather than △Nit. Dynamic stressing enables us to have a more realistic and precise vision in the estimation of device reliability. And we found that the trapping effect is responsible for the transistor degradation. Under NBTI, we found that the trapping effect is larger than the reaction-diffusion model.
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Figure-Chapter 1
Fig. 1-1 With the marching of technology nodes, gate dielectric has to be shrunk and five silicon atoms thick of gate dielectric is predicted for 2012.[1]
Fig. 1-2 Measured and simulated Ig-Vg characteristics under inversion condition for nMOSFETs. The dotted line indicates the 1A/cm2 limit for the leakage current. [2]
Fig. 1-3 Several high-k gate dielectric materials with their bandgaps and dielectric constants.[3]
Fig. 1-4 Several high-k gate dielectric materials with their band offsets.[4]