Low Noise Amplifier Design Methodology

A common gate CMOS low noise amplifier with a regulated cascode active inductor load and a source follower negative conductance generator will be presented in this section.

In order to improve the power gain of the low noise amplifier, a large impedance of the load is required. Thus, the current running on the impedance should be minimized for obtaining a large impedance load, and the size of transistor can also be minimized. Moreover, the dimension of transistors should be increased to generate a large bias current for obtaining good linearity. Therefore, trade-offs between the power gain and linearity should be taken into account. An alternate configuration, combining with the regulated cascode active inductor and the source follower negative conductance generator are used to increase the impedance load. In other words, increasing the Q-value of the active inductor can obtain the large impedance load. In order to increase the Q-value, the loss of the active inductor should be reduced. The source follower negative conductance generator generates the negative conductance (–Gn) connected in parallel with the active inductor. The loss of the active inductor can be reduced.

Therefore, a low noise amplifier, which has the features of higher gain, smaller chip size, and lower power consumption, is proposed. The configuration of the proposed low noise

amplifier consisting with four signal-processing stages is illustrated in Fig. 3.4.

Fig. 3.4 The proposed low noise amplifier

In Fig. 3.4, the first stage, transistors M1 and M2 comprise the input amplifier stage.

This common-gate configuration provides a simple 50-Ohm input impedance matching and higher linearity in contrast to a common-source configuration without source degeneration.

This common-gate configuration also helps to increase the effective reverse isolation in heterodyne architectures due to the signal leakage of the local oscillator from the mixer to the antenna. The second stage, a regulated cascode active inductor is constructed by transistorsM3, and M7~M11. The regulated cascode active inductor acts as the load of the low noise amplifier. The equivalent circuit model of the active inductor is shown in Fig. 3.2. The source follower negative conductance can help reduce the inductor loss of the regulated

M11 are formed the active inductor constant current source. The third stage, a source follower negative conductance generator is constructed by transistors M4~M6. The main idea of this stage is to generate an out-of-phase current respected to the input current and feed it back to the input voltage at the same node called the negative conductance generator, which compensates the loss of the active inductor. Therefore, it is possible to improve the quality factor of the active inductor. The final stage, the output voltage buffer is built up by transistors M12 and M13. A voltage buffer follows the designed amplifier in order to drive a 50-Ohm resistive load and it also requires a large drain current to drive a low resistance load.

The transistors of MN1 to MN3 produce the bias voltage to provide the voltage the transistors M1, M4, M9, M11, and M12. The capacitors of the C1 and the C2 are the dc coupling to block the dc voltage so that the external bias voltage will not affect the bias of the amplifier.

3.1.4 Simulation Results

The low noise amplifier was simulated by parameters from a standard CMOS 0.35-um digital process technology using HSPICE simulator. The normal supply voltage is 3.3V. Figs.

3.5, 3.6 and 3.7 show the simulation results of S21, S11, S12, S22, and noise figure where the amplifier is tuned around 2GHz. It can be seen that S21 is 17.6dB and S11, S22, and S12 are –11.2dB, -11.9dB, –39.4dB, and 5.05dB around 2GHz, respectively.

In RF amplifier, the conditions (necessary and sufficient) for unconditional stability are expressed in following:

2

12 21 1 22

S S < − S

From Fig. 3.5 and 3.6, at f = 2GHz, we find that K = 1.31 and D = 0.174∠160 ﾟ. Since K > 1 and |D| <1, the amplifier is unconditional stable. Furthermore, in the frequency range between 1.6GHz and 2.4GHz shows the K > 1 and |D| <1, the amplifier will be unconditional stable.

The 1dB compression and the IIP3 are -26dBm and -13dBm, respectively, and are shown in Fig. 3.8 and Fig. 3.9. From Fig. 3.8 and 3.8, the linearity of the proposed amplifier can achieve reasonable requirements. The layout of the low noise amplifier is shown in Fig.

3.10. From Fig. 3.10, the area of the proposed circuit is 108um×104um, which is smaller than that of the amplifiers use the passive spiral inductor of the previous work. Furthermore, the power consumption of the low noise amplifier is 21.4mW, which is smaller than that others design. A comparison between our design using the regulated cascode active inductor with the negative conductance generator of source follower configuration and other designs reported in the literature is presented in TABLE 3.1.

Fig. 3.6 S22 and S12 of the low noise amplifier

0 2 4 6 8 10 12

1.6E+09 1.7E+09 1.8E+09 1.9E+09 2.0E+09 2.1E+09 2.2E+09 2.3E+09 2.4E+09 Frequency

dB

Noise Figure

Fig. 3.7 Noise figure of the low noise amplifier

-30 -20 -10 0 10

-40 -35 -30 -25 -20 -15 -10

Pin, dBm

Pout, dBm

1 dB Compression

Fig. 3.8 1dB compression of the low noise amplifier

IIP3

-40 -30 -20 -10 0 10

-35 -30 -25 -20 -15 -10

Pin, dBm

Pout, dBm

1st Main Signal

3rd Signal

Fig. 3.9 IIP3 of the low noise amplifier

VDD!

gnd!

Vin

V1

Vout Current

Source NCG

Buffer

Regulated Active Inductor Common

Gate Amplifier

Fig. 3.10 Layout of the low noise amplifier

3.1.5 Discussion

This work presents the design of a CMOS low noise amplifier using the regulated cascade active inductor and the source follower negative conductance generator as the frequency selective element and the Q-enhancement. The proposed circuit is verified by HSPICE simulation and the results show that the center frequency and the power gain of the low noise amplifier are electronically tunable. The performance of the low noise amplifier is better than that of the integrated passive inductor. The achievement of this work is to reduce the size of the chip to 108um×104um.

TABLE 3.1 COMPARISONS OF 2 GHZ LOW NOISE AMPLIFIERS

Karanicolas(20) Texas A&M(32) Thanachayanont(34) This work Technology 0.5um CMOS 0.5um CMOS 0.8um BiCMOS 0.35um

Gain (dB) 15.6 20.5 23 17.6

Frequency (Hz) 900M 1G 900M 2G

Power (mW) 20 14 50 21.4

1 dB (dBm) NA NA -24.3 -26

IIP3 (dBm) -3.2 -12.4 -27 -13

NF (dB) 2.8 3.65 4.3 5.05

Inductor On chip spiral Active Active Active

Area (mm²) 0.28 0.08 NA 0.012

3.2 A 2.4GHz CMOS Low Noise Amplifier with High-Q