Layout Consideration and Post-layout Simulation

Chapter 4 System Level Design…

5.6 Layout Consideration and Post-layout Simulation

Because CTSDM is essentially a mixed-signal system, many design issues must also be considered in layout level implementation. The modulator contains continuous-time blocks such as loop filter, sampled data blocks such as the quantizer, and purely digital blocks such as latch and encoder. In order to achieve high resolution as well as high linearity, several techniques such as common-centroid layout for current source and capacitors, inter-digitation for transistors, guarding ring and shielding must be used to reduce the performance loss due to mismatch, parasitic and non-linearity.

In loop filter layout, fully symmetrical layout style is employed for the differential signal path. To improve the matching, dummy capacitors are added in MIM capacitor array to make the environments of all unit capacitors the same. Except for the tunable capacitor array to compensate the time constant variation, crossed resistors technique is also employed to reduce the mismatch of the passive device.

current-steering DAC. While in layout level, symmetrical sequence technique [7] is employed to further reduce linear gradient errors. As illustrated in Fig. 5.15, all even-numbered current cells are placed on one side of the array center, while odd-numbered ones are placed on the other side. In the way, linear gradient errors are cancelled by every two cells located symmetrically about the center.

Fig. 5.15 Current-steering DAC layout with symmetrical sequence

The whole chip layout and die photo of the proposed CTSDM is shown in Fig.

5.16.

Fig. 5.16 Layout of the proposed CTSDM and chip die photo

The post-layout simulation result is shown as following: Fig. 5.17 is the FFT of the modulator output. The summary of Fig. 5.17 is shown in Table 5.5.

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(a) Fin = 3.203125 MHz (b) Fin = 8.671875 MHz Fig. 5.17 FFT of the post-layout simulation result

Table 5.5 Summary of the post-layout simulation result Signal Bandwidth = 10 MHz FFT points = 4096 CLK = 320 MHz

Fin = 3.203125 MHz Fin = 8.671875 MHz

SNDR 79.31 dB SNDR 79.37 dB

ENOB 12.88 ENOB 12.89 The comparison of pre-layout and post-layout simulation is shown in Table 5.6.

Table 5.6 Comparison of the pre-layout and post-layout simulation result

Pre-sim Post-sim

Technology TSMC 0.18 μm

Supply voltage 1.8 V

Signal Bandwidth 10 MHz

Sampling frequency 320 MHz(OSR=16)

Peak SNR 83.29 dB 80.94 dB

Peak SNDR 81.97 dB 79.31 dB

ENOB 13.32 12.88

Power consumption 36.1 mW 35.5 mW

Chip Area 0.993 × 1.113 mm²

Core Area 0.680 × 0.440 mm²

figure of merit defined as:

(

fJ conversion

BW Power

FOM

_ENOB

⋅

= ⋅ (5.7)

Table 5.7 Comparison of this work and previous researches

Tech

From Table 5.7, we can find out that most previous papers only focus on high resolution (SNR>80 dB) or high bandwidth (BW>10 MHz) performance, while the proposed CTSDM achieves ENOB of 12 bits with 10 MHz bandwidth at the same time, and the power consumption is relative low. In FOM comparison, [6] only showed the simulation result and the architecture is simpler (1-bit quantizer). The process of [5] is more advanced than this work and the supply voltage is 1.2V. Take

[28] with FOM’=235*(0.13/0.18)²=123(fJ/conversion), which is almost the same as [5]. In Table 5.8 and Fig. 5.18, the comparison of CTSD- and pipelined ADC are shown. According to [15], the power consumption of decimator is relatively low compared with modulator in SD-ADC, but significant. We assume the worse case that the power consumption of decimator is the same as modulator. Nonetheless, the achieved FOMs of CTSD-ADC still show better performance compared with pipelined ADC.

Table 5.8 Comparison of CTSD- and pipelined ADC

2844 [5] 2006 JSSC

460 [6] 2007 TCASI*

4866 [1] 2004 JSSC

4364 [35] 2009 JSSC

1847 [34] 2006 TCASI

814 [33] 2005 JSSC

4477 [31] 2004 JSSC

FOM [5] 2006 JSSC

460 [6] 2007 TCASI*

4866 [1] 2004 JSSC

4364 [35] 2009 JSSC

1847 [34] 2006 TCASI

814 [33] 2005 JSSC

4477 [31] 2004 JSSC

FOM

SNDR VS Power

0

Fig. 5.18 Comparison of CTSD- and pipelined ADC

conclude that for the high requirements of ADCs in the future, CT ΣΔADCs can be an alternative to Nyquist ADCs to achieve higher performance with lower power consumption.

Chapter 6 Test Setup and Experimental Results

_________________________________________

This chapter describes the test setup and experimental results of the prototype chip. Because of the high speed operation of the proposed CTSDM, the printed circuit board (PCB) for the test chip must be designed carefully. The test environment of this work is also introduced. Finally, the measurement results and discussion are presented.

_____________________________________________________________________

6.1 Test Board Design

To achieve the expected performance and high speed operation of the prototype chip, the test board must be designed for many considerations. The two-layer PCB for the test chip is shown in Fig. 6.1. The top layer is used to place components such as regulators, variable resistors, capacitors and switch. The bottom layer is the ground plane. To avoid the parasitic effect of the package in high speed operation, the raw die is directly connected to PCB by bonding wires. The analog and digital powers are both provided by LM1117 fixed output regulator combined with battery series as shown in Fig. 6.2(a), and they are isolated into different partition on PCB to prevent the noise in digital circuits coupling to the analog ones through the supply paths. The output of regulator is decoupled by a 10 μF tantalum capacitor for the lower-frequency noise, and high-frequency noise are decoupled by capacitors of 0.1 μF and 0.01μF placed at each supply pin of the prototype chip. In addition to the

for DAC latches are provided by LTC3025 VLDO (very low drop-out) linear regulator as shown in Fig. 6.2(b). The power and ground traces are made as short as possible to minimize the wire resistance.

(a) (b)

Fig. 6.1 Top layer and bottom layer of the PCB

LM1117

Vin Vout

GND 10uF

Tantalum 10uF

Tantalum

BIAS

SHDN OUT

ADJ

GND

V_OUT=0.4V(1+R₂/R₁)

R₂

R₁

C_OUT LTC3025

(a) (b)

Fig. 6.2 Typical application of LM1117 and LTC3025 regulator

combined with retention module on PCB is used to minimize the equivalent load. The differential signal traces are routed symmetrically. The inputs of modulator and clock source are placed as close as possible to the chip. The high frequency digital traces are also as short as possible to reduce electromagnetic interference.

6.2 Test Environment Setup

Vector Signal Generator

R&S SMU200A

Power Splitter

Bias-Tee DUT

Signal Generator

320MHz CLK

Power Supply Battery and

Regulator 1.8V 3.3V

R&S SML03

Logic Analyzer

Agilent 16902A 10 MHz

sine wave

Fig. 6.3 Test environment

Fig. 6.3 is the test environment of the test chip. The input signal and 320 MHz clock of the modulator are generated by Rohde & Schwarz signal generator. The single-ended input signal is transformed into differential on by power splitter and bias-Tee, then it is fed into the chip through SMA connector on PCB. The power supply for the chip core is 1.8V, and the supply voltage of LTC3025 is 3.3V. Both these two powers are provided by LM1117 regulators. The modulator outputs are sampled by Agilent logic analyzer (LA) through retention module on PCB and connetorless probe. The acquired data in LA then transferred to the computer and analyzed by MATLAB. The test environment and PCB photo are shown in Fig. 6.4.

(a) (b)

Fig. 6.4 Test environment and PCB photo

6.3 Measurement Results

6.3.1 The Tuning Mechanism of the Proposed CTSDM

There are two ways to tune the loop filter coefficients in the proposed CTSDM:

the tunable capacitor array (TCA) and the feedback current biased by external power supply as shown in Fig. 6.5. As described in Chapter 5, the TCA is controlled by a 3-bit binary code by switch on PCB to change the Cin-use for the modulator. The Cmin is set to be 0.6pF and C’ is 0.1pF for reasonable tuning range. If there is no any process variation for the resistors and capacitors in the continuous-time loop filter, the switch code of “100” should result in the measurement result the same as the simulation one.

However, the RC time constant of the practical integrators can vary by as much as more than 30% due to the PVT variation, which will greatly reduce the noise shaping effectiveness and even drive the loop filter unstable [8]. To compensate this large variation, what we can do is to tune the capacitor array and feedback bias current, in other words, to change the undesired loop filter coefficients back to the original one.

sTs

Fig. 6.5 Tuning mechanism of proposed CTSDM

As shown in Fig. 6.5, there are three sets of TCA in proposed CTSDM and they are controlled by the same binary code. In simulation level, the switch code of “100”

means that the Cin-use is 1 pF, and the ideal loop filter coefficient (ki) can be obtained:

i i S i i i S

k f R C

C f R

k

= 1 ⇒ = 1 (6.1)

But in real implementation, the RC time constant will change greatly due to process variation as well as the loop filter coefficients. For example, if the loop filter coefficient in real implementation (kir) is larger than ideal one, which means that the real RC time constant (RirCir) is smaller than the ideal one, than we can increase the binary code by one bit to obtain a larger Cin-use as well as RirCir. Consequently, the real RC time constant is more close to the ideal one and the system becomes more stable.

On the other hand, RirCir can also be smaller by decreasing the binary code of the switch if the noise shaping effectiveness is worse than ideal one due to the smaller kir.

Thanks to the TCA mechanism, the proposed CTSDM can also work with lower sampling clock if the measurement results show that the chip can not operate with such a high sampling frequency.

the current produced by feedback DACs represent the feedback coefficients of the loop filter. Any mismatch of feedback and feed-forward coefficients could lead to unstable system. In this work, the three bias current of the DACs are provided by a single variable resistor with external power supply voltage, so the current is tunable.

In some case that the TCA can not compensate RC time constant variation effectively, the tuning of feedback current can be another solution. Here, the tuning range of the feedback current is set to be ±50% according to the TCA limitation and the normal operation of the bias circuit.

6.3.2 Measurement Results

Nine chips are test in this work. The test principle of the prototype chip is as following: first, we assume that there is no nay process variation occurred, so the switch code is set to be “100”, resulting in the bias current of feedback DACs is 30 μA. The signal amplitude of modulator input is 110 mV, the same as in simulation. If the modulator output is saturated, which means that the system is unstable, we increase the switch code to decrease the loop filter coefficient as well as more stable condition. Finally, we change the input swing to achieve better performance or more stable operation of the modulator.

The measurement results show that the prototype chip can not work correctly as simulation results. Although in some tuning case that the noise shaping can be observed in output spectrum, the noise floor is still too high, so the expected SNDR can not be achieved. The outputs of modulator are almost all saturated when the bias current of feedback DACs is 30 μA (normal condition) with switch code from “000”

to 111, which means that the process variation may be larger than the tuning range we

input frequency of 3 MHz and 8 MHz are shown in Fig. 6.6, and the comparison of measurement and simulation results is shown in Table 6.1.

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(a) (b) Fig. 6.6 Output spectrum of measurement results

Table 6.1 Comparison of measurement and simulation results

Pre-sim Post-sim Measurement

Technology TSMC 0.18 μm

Supply voltage 1.8 V

Signal Bandwidth 10 MHz

Sampling frequency 320 MHz(OSR=16)

Peak SNR 83.29dB 80.94 dB 22.55 dB

Peak SNDR 81.97dB 79.31 dB 22.38 dB

ENOB 13.32 12.88 3.43

Power consumption 36.1mW 35.5 mW 37.17 mW

Layout Area 0.993 x 1.113 mm²

According to the measurement compared with simulation results, the possible problems of the prototype chip are discussed in the following.

6.4 Discussion

6.4.1 The Noise Problem

To find out the problems about the incorrect work of the prototype chip, the real waveform of digital output must be checked as well as the supply voltage for the chip powers. The 4-bit digital output can be observed through logic analyzer directly, and we can compare the waveform of these data with ideal simulation results to verify that whether the chip working is correct or not. The unsaturated 4-bit digital output of measurement is shown in Fig. 6.7(a). Compared with the output waveform of simulation in Fig. 6.7(b), it is obvious that there are too many ripples occurred in MSB (B4) of measurement results, hence the noise floor will be very high in output spectrum deservedly.

B4(MSB)

(a) (b) Fig. 6.7 Comparison of measurement and simulation output

4-bit binary code back to the corresponding analog waveform (Fig. 6.8(a)) and compare it with the ideal one in simulink simulation (Fig. 6.8(b)). As shown in Fig.

6.8(a), although it seems that the continuous-time integrators inside the chip can work and the output of the third integrator of the modulator are converted to 4-bit binary code successfully, the ripples are still too high compared with the ideal output.

3.175 3.18 3.185 3.19

x 10⁴ 0

5 10 15

4 4.5 5 5.5 6 6.5

x 10-6 -0.8

-0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8

Time offset: 0

(a) (b)

Fig. 6.8 Comparison of measurement and simulation output in MATLAB

Fig. 6.9 Output waveform of digital output in oscilloscope

oscilloscope, as shown in Fig. 6.9, we can find out that the undesired logic 1 of MSB are also occurred. Because the waveform in oscilloscope represents the output from the chip on PCB directly, the noise problem is indeed caused by the chip itself.

As shown in Fig. 6.9, except for the large noise occurred while the digital output must be logic 0, the threshold uncertainty of logic 1 is also very large. The possible reason for this large spike is the power line noise. To check the transient response of the dc supply voltage, we use oscilloscope to observe the real waveform of the supply voltage on PCB pins similarly. As shown in Fig. 6.10, the power line noise in digital powers is very large. The amplitude of the noise is about 50 mV, and the frequency is about 320 MHz, which is the same as the sampling frequency for the chip. Due to the coupling effect, other supply voltage such as analog powers and reference voltage for internal ADC are also not clean. From the observing in oscilloscope, the amplitude of other power lines noise is almost the same. This high speed power line noise will degrade the modulator performance and even make the system unstable.

Fig. 6.10 Output waveform of digital supply voltage in oscilloscope

are discussed as following.

6.4.2 RC Variation Consideration

The large ripples discussed in 6.4.1 can be caused by two reasons: incorrect operation of internal modulator and high speed noise coupled by power line of the output digital circuits. From the measurement results discussed in 6.3.2, we suspect that the process variation is larger than the tuning range we designed, so the original loop filter coefficients can not be obtained to achieve the ideal noise shaping effect and the modulator can not work correctly. In MATLAB, the time constant error due to the process variation can be modeled as a gain error of the integrator. By simulink model simulation, we can find out the range that the proposed CTSDM suffered from RC variation can still work correctly with TCA compensation. Here, the trend of RC variation for all integrators is set to be the same. As described in Eq. 6.1, the ideal coefficients are named by ki. Taking the RC variation into account, the real coefficients kir are different form the ideal ones, and we can represent kir combined with ki and a variation term, ΔRC, as shown in Eq. 6.2. Finally, the TCA compensation is also considered, and the effectiveness of the compensation is denoted by ΔTCA. The overall equivalent loop filter coefficients are represented by k’ir, and the equation covering RC variation and TCA compensation is shown as Eq. 6.3.

) the range between -50% to +50%. The summary of MATLAB simulation results are listed in Table 6.2.

Tuning range of this work

Resistor variation according to TSMC model

Table 6.2 Summary of MATLAB simulation results with RC variation and TCA Compared with MATLAB simulation, the proposed tuning range is indeed sufficient to cover the RC variation in TSMC process.

6.4.3 Power Supply Noise Effect

Due to the high speed operation of the digital circuits, the coupling effect must be considered. From RC-extraction of layout, the coupling capacitors between different power line buses can be found. As shown in Fig. 6.11, although the noise coupled by DVDD2 (digital powers) crossed over VREF1 and VREF2 can not be observed in post-layout simulation, the real coupling effect can be calculated and verify by adding this noise to spice simulation.

Fig. 6.11 Crossed over power line buses

For example, the coupling capacitors (Cc) between DVDD2 and VREF1, VREF2 are 3.2 fF and 4.3 fF, respectively, while Cc between ground and VREF1, VREF2 are 0.7 fF and 0.8 fF. Assume the noise source coupled by DVDD2 is a small signal of 320 MHz frequency and 50 mV amplitude, the noise coupled to VREF1 and VREF2 can be calculated:

The order of the noise amplitude is almost the same between calculation and real waveform observed in oscilloscope. The other noise coupled by DVDD2 can also be calculated in the same way. In spice simulation, we set all the noise source amplitude is the same as that of DVDD2, and the coupled effect can be observed directly.

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Fig. 6.12 Hspice simulation results of coupling noise effect

In pre-layout simulation, although the small signal noise is added to every power supply voltage source, the output spectrum is almost the same as the one without any noise. But in post-layout simulation which considering all the parasitic and coupling capacitors, the influence due to the large noise in power line is obvious. Fig. 6.12 is the 1024-points FFT output spectrum of post-layout simulation results with coupling noise effect. In Fig. 6.12(a), there is no any coupling noise in power lines, and the achieved SNDR is more than 74 dB (ENOB>12 bits). In Fig. 6.12(b), the digital power and reference voltage of flash ADC are added by a noise small signal source, while the noise floor of output spectrum raise largely, resulting in the degraded SNDR

a small signal noise, and the achieved ENOB is only 4.25 bits. The noise floor (~-40dB) in Fig. 6.12(c) is almost the same as that of measurement results. From the simulation result with coupling noise, the reason why the prototype chip can not work correctly can be explained. Because of the high speed noise coupled by digital power line bus, not only the analog block can not work correctly, due to the variation of the reference voltage, the internal flash ADC can not convert the analog output of the third integrator to digital code precisely, and the linearity of feedback DAC is also decreased. Thus, the modulator becomes unstable and the SNDR degrade quickly.

6.4.4 Summary of the Problems of Proposed CTSDM

From the aforementioned discussion, the main problems of the proposed CTSDM are summarized as following:

Tuning Range Limitation

z Compared with measurement and MATLAB simulation, the proposed tuning range is sufficient to cover the RC variation in real implementation.

High speed power line coupling issue

z By observing the output data in oscilloscope, the threshold uncertainty due to noise coupled by power line and RC variation is very large.

在文檔中一個時脈為320MHz訊號頻寬10MHz之十二位元CMOS連續時間積分三角調變器 (頁 63-0)