I NSTRUCTION S ET

Our instruction set architecture is similar to MIPS. Each instruction is 32 bits long that

divided into several fields. The instructions can be classified into two categories as following:

 R-type operations

 I-type operations

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Table 3.2 shows the instruction format and Table 3.3 lists our available instructions.

5 bits 5 bits 5 bits 5 bits 5 bits 6 bits 1 bit

R-type/MAC Opcode Rd Rs Rt Shamt Funt P bit

I-type Opcode Rd Rs Immediate P bit

Table 3.2 Instruction Format

The meaning of each fields of instruction format is described in the following:

 Opcode: Operation code. It indicates which operation is performed.

 Rd: The register destination operand. The result of instruction is stored to this register if

need.

 Rs: The first source operand of instruction.

 Rt: The second source operand of instruction.

 Shamt: The amount of shift is specified in this field. It specifies the shift operations are

going to shift source operand with values.

 Funt: It is used to indicate which operation of R-type instructions is performed. If the

executing instruction is I-type instruction, this field is filled with 0.

 P bit: It implies whether current operation can be executed with other operation in

parallel. 1: means can be executed in parallel with other operation.

 Immediate: An immediate value for I-type instructions.

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Note:

 R-type instruction includes all of arithmetic operations. They have the same opcode. The

operation of R-type instruction is executed according to Funt field.

 The special instruction type, MAC, has the same instruction format with R-type

instruction.

 The three fields, Rd, Rs and Rt, are 5 bits because there are 32 registers in our

implementation.

 The shamt field has the similar reason because the registers are 32 bits.

Instruction Description 32-bit instruction word

NOP - 00000000000000000000000000000000

MAC operations

MAC $0, Rs, Rt Acc = Acc + Rs.L*Rt.L 1001100000sssssttttt00000010000p ACCLDH Rd Rd = Acc[39:32] 10011ddddd000000000000000010001p ACCLDL Rd Rd = Acc[31:0] 10011ddddd000000000000000010010p

ALU operations

ADD Rd, Rs, Rt Rd = Rs + Rt 00001dddddsssssttttt---000000p ADDU Rd, Rs, Rt Rd = Rs + Rt

(Unsigned)

00001dddddsssssttttt---000001p SUB Rd, Rs, Rt Rd = Rs – Rt 00001dddddsssssttttt---001000p SUBU Rd, Rs, Rt Rd = Rs – Rt

(Unsigned)

00001dddddsssssttttt---001001p AND Rd, Rs, Rt Rd = Rs & Rt 00001dddddsssssttttt---010000p OR Rd, Rs, Rt Rd = Rs | Rt 00001dddddsssssttttt---010001p XOR Rd, Rs, Rt Rd = Rs ♁ Rt 00001dddddsssssttttt---010010p MIN Rd, Rs, Rt Rd = min(Rs, Rt) 00001dddddsssssttttt---101000p MAX Rd, Rs, Rt Rd = max(Rs, Rt) 00001dddddsssssttttt---110000p ABS Rd, Rs, $0 Rd = |Rs| 00001dddddsssssttttt---111000p SLT Rd, Rs, Rt If (Rs < Rt) Rd = 1 00001dddddsssssttttt---100000p SRL Rd, Rs, shamt Rd = Rs >> shamt 00001dddddsssssttttt---011000p SRA Rd, Rs, shamt Rd = Rs >> shamt (sign 00001dddddsssssttttt---011001p

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extend)

NOT Rd, Rs, $0 Rd = Rs + $0 00001dddddsssssttttt---111010p ADDI Rd, Rs, imm Rd = Rs + imm 00010dddddsssssiiiiiiiiiiiiiiiip ADDIU Rd, Rs, imm Rd = Rs + imm

(unsigned)

00011dddddsssssiiiiiiiiiiiiiiiip SUBI Rd, Rs, imm Rd = Rs – imm 00100dddddsssssiiiiiiiiiiiiiiiip ANDI Rd, Rs, imm Rd = Rs & imm 10000dddddsssssiiiiiiiiiiiiiiiip ORI Rd, Rs, imm Rd = Rs | imm 10001dddddsssssiiiiiiiiiiiiiiiip XORI Rd, Rs, imm Rd = Rs ♁ imm 10010dddddsssssiiiiiiiiiiiiiiiip

Data transfer operations

MOV Rd, Rs Rd = Rs + $0 00001dddddsssssttttt---000100p MOVI Rd, $0, imm Rd = imm + $0 01110dddddsssssiiiiiiiiiiiiiiiip

MOV.l Rd, Rs Rd.L = Rs.L + $0 00001dddddsssssttttt---000101p MOV.h Rd, Rs Rd.H = Rs.H + $0 00001dddddsssssttttt---000110p LW Rd, Rs, imm Rd = Mem[imm+Rs)] 11000dddddsssssiiiiiiiiiiiiiiiip SW Rd, Rs, imm Mem[imm+Rs) = Rd] 11100dddddsssssiiiiiiiiiiiiiiiip

Branch operations RETURN $ra Jump to address in $ra 0101000000000110000000000000000p

CALL imm Save PC to $ra and

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MIN.D Rd, Rs, Rt Rd.H = min(Rs.H, Rt.H);

Rd.L = min(Rs.L, Rt.L);

00001dddddsssssttttt---101001p

MAX.D Rd, Rs, Rt Rd.H = max(Rs.H, Rt.H);

Rd.L = max(Rs.L, Rt.L)

00001dddddsssssttttt---110001p

ABS.D Rd, Rs, $0 Rd.H = |Rs.H|;

Rd.L = |Rs.L|

00001dddddsssssttttt---111001p

Table 3.3 Instruction Set

There are also several special instructions used for single-instruction multiple-data (SIMD) application. We can improve the throughput of pipeline with data level parallelism via SIMD operations. We have nine instructions for SIMD application. They are described as

following.

5 bits 5 bits 5 bits 5 bits 5 bits 6 bits 1 bit

Opcode Rd Rs Rt shamt funt End bit

The instructions used for SIMD application have same instruction format with R-type instructions. PACK instruction packs two 16-bit data into a 32-bit register. The funt field of PACK instruction is separated into two portions, the first half of funt field indicates the first or

the last half of Rs will be packed into Rd, the last half of funt field is used for Rt. As Figure 3.3 shows, the 16-bit data from the first or the last half of Rs will be packed into the first half of Rd, and the 16-bit data from Rt will be packed into the last half of Rd.

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Rs

Rt Rd

Figure 3.3 PACK instruction

UNPACK instruction unpacks two 16-bit data in Rd into Rs and Rt. Because there is one

write bus in our implementation, we have to use two UNPACK instructions to unpack the two 16-bit data. Fortunately, these two unpack instruction can be executed in parallel due to two-way VLIW design. ADD.D and SUB.D instructions perform two 16-bit add or subtraction operations in parallel. ADDU.D and SUBU.D instructions perform the same operations with ADD.D and SUB.D, but the source data of ADDU.D and SUBU.D is unsigned value. MIN.D

and MAX.D instruction select the minimum or the maximum respectively. ABS.D instruction calculates the absolute value of two 16-bit values located in the first and last half of Rs. These instructions are executed in the first and last half of sources. Then, the outcomes are placed in

destination register at same time.