Optimized Scaling Behavior for 8192-point FFT

Table V presents the scaling behavior for 8192-point, radix-2 FFT with different wordlength (WL), and the input signals are uniformly distributed in [-1, 1] with <1, WL-1>

number format. The runtime of the optimization flow is from 0.04 seconds to 127.2 seconds for 8 to 16 bits of wordlength. Since the major computation is the convolution at each stage, the time complexity is O(2^WL*s), where s is the number of stages. We can find that the SQNR of our result is much higher than Oppenheim’s approach [12]. Fig. 28 shows that the wordlength has about 3 bits less than Oppenheim’s approach with the same SQNR.

Therefore, about 48k (3*8k*2, for both real and imaginary parts) bits of storage can be saved by our approach. And compared to BFP approach [1], the performance of our method is almost the same without the high hardware complexity for dynamic scaling method.

Table V Scaling behavior for 8192-point, radix-2 FFT

WL

(bit)

Integer Part of Each Stage SQNR

(proposed)

SQNR

[12]

1 2 3 4 5 6 7 8 9 10 11 12 13 Runtime

(sec)

8 2 3 4 4 5 5 6 6 7 7 8 8 9 0.04 18.08 dB -3.75 dB

9 2 3 4 4 5 5 6 6 7 7 8 8 9 0.06 23.70 dB 2.14 dB

10 2 3 4 5 5 6 6 7 7 8 8 9 9 0.07 27.47 dB 8.11 dB

11 2 3 4 5 5 6 6 7 7 8 8 9 9 0.11 33.47 dB 14.10 dB

12 2 3 4 5 5 6 6 7 7 8 8 9 9 1.60 39.50 dB 20.13 dB

13 2 3 4 5 5 6 6 7 7 8 8 9 9 3.52 45.51 dB 26.15 dB

14 2 3 4 5 5 6 6 7 7 8 8 9 9 18.36 51.50 dB 32.16 dB

15 2 3 4 5 5 6 7 7 8 8 9 9 10 44.44 55.28 dB 38.18 dB

16 2 3 4 5 6 6 7 7 8 8 9 9 10 127.2 60.83 dB 44.18 dB

-10.00 0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00

8 9 10 11 12 13 14 15 16

SQNR (dB)

wordlength (bit)

Oppenheim [12]

BFP [1]

proposed 3 bits

Fig. 28 SQNR vs. wordlength for 8192-point, radix-2 FFT

The comparison of 11-bit and 14-bit wordlength for 8192-point, radix-2 FFT processor are given in Table VI. The FFT architecture is memory-based and synthesized in 10 ns of cycle time, which gives 100M Sample per second of throughput. The SQNR of the one with 11-bit wordlength by our proposed method is almost the same as the other one with 14-bit wordlength by Oppenheim’s approach as shown in Fig. 28. The area and power reduction excluding storage is 33.65 % and 26.89 %, respectively, as well as the storage reduction is 21.41 %.

Table VI Hardware Comparison of 11-bit and 14-bit wordlength for 8192-point, radix-2 FFT

8192-point radix-2 FFT (100MS/s)

11-bit WL 14-bit WL Reduction

Area excluding storage 85,771.2 μm² 129.852.7μm² 33.65 % Power excluding storage 1.9229 mW 2.6302 mW 26.89 %

Storage 180k bits 229k bits 21.41 %

Fig. 29 shows the SQNR with different wordlengths for 8192-point, radix-4 FFT. Also 3-bit benefit is obtained with our method as compared to Oppenheim’s scheme. Note that Ramakrishnan’s approach [13] is not suitable for inputs with uniform distribution, so the error performance is not good under this assumption. The case of radix-8 FFT is shown in Fig. 30.

Moreover, about 4-bit wordlength can be saved in this algorithm.

-10.00

Fig. 29 SQNR vs. wordlength for 8192-point, radix-4 FFT

-10.00

Fig. 30 SQNR vs. wordlength for 8192-point, radix-8 FFT

For the inputs with normal distribution, Fig. 31 and Fig. 32 show the experimental results of deviation σ= 0.2 and 0.4. When σ= 0.2, our analyzed results from 10-bit to 15-bit wordlength is the same as these of Ramakrishnan’s approach, which are increasing 1 bit for each radix-4 stage. However, Ramakrishnan’s approach is not feasible when σ= 0.4, while our method still has good performance. Fig. 33 shows the SQNR for different deviations with 12-bit wordlength, and we can find that Ramakrishnan’s approach is only feasible in a narrow range. Expect the performance is the same at σ = 0.2, our approach is better than Ramakrishnan’s method in all the other cases.

-20.00

-10.00

Fig. 32 SQNR vs. wordlength for 8192-point, radix-4 FFT with normally distributed inputs (σ= 0.4)

0.00

Fig. 33 SQNR with different deviations for 8192-point, radix-4 FFT with normally distributed inputs (WL = 12)

Chapter 5

Conclusion & Future Work

In this thesis, a fast precision optimization approach to fix the scaling behavior at each stage which gives optimized SQNR is proposed for the FFT processor design with the fixed-wordlength storage. This method is based on the probability-based analysis which utilizes the concept of the derived distribution. It has ability to evaluate the overflow and truncation behavior in terms of probability and induced noise at each stage. The proposed flow can handle different FFT sizes, input distributions, algorithms, and wordlengths of storage. The experimental results show that about 3 bits of wordlength for 8192-point radix-2 FFT processor can be saved compared to Oppenheim’s approach [12] without any hardware overhead. Furthermore, the wordlength can be saved about 4 bits for 8192-point, radix-8 FFT.

Area and power consumption can be further reduced significantly. The performance is also comes close to the dynamic scaling method [1], that is, the SQNR difference is within 2 dB which is about 1/3 bit for the same wordlength.

In the future, more designs for DSP, such as FIR filters, can be analyzed by the concept of derived distribution to optimize the wordlength. The scaling decision is a good guideline for design automations and optimizations.

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Vita

Ming-En Shih was born in Hsinchu, R.O.C., on February 1, 1987. He received the B.S.

degree from the Electronic Engineering Department from National Chiao Tung University in June, 2009. He is the graduate student of Prof. Jing-Yang Jou. His research interests include digital hardware design, digital signal processing, and Electronics Design Automation (EDA).