Organization

This paper is divided into four chapters:

Chapter 1: Introduction.

Chapter 2: Experimental Procedures and Characteristics of Sol-Gel Processed.

Chapter 3: Fabrication Procedures of the InGaAs/InAlAs MOS-MHEMT.

Chapter 4: The Performance of the InGaAs/InAlAs MOS-MHEMT.

Chapter 5: Conclusion and Future Works.

The organization chart of this thesis is exhibited in Fig 1-1. Chapter 1 shows the background, motivation and organization of this thesis. Chapter 2 shows the preparation of sol-gel processed TiO2, we will describe the fabrication procedures of the InGaAs/InAlAs MOS-MHEMT in chapter 3. In chapter 4, we will discuss the DC characteristics of MHEMT which compared with MOS-MHEMT, the finally conclusion and future work of this study will discuss in Chapter 5.

Fig. 1-1 The organizational chart of this study.

Chapter 2

Experimental Procedures and Characteristic of Sol-Gel Processed

The experimental procedures of solution-gelation (sol-gel) processed titanium dioxide (TiO2) are prepared using the equipment consists of a dropper, a phial, a magnetic stirrer, a stirrer bar, further depositing by spin casting and baking.

The sol-gel systems in this study show in Figs. 2-1, 2-2 and 2-3. The flowchart about experimental procedures of sol-gel processed TiO2 is exhibited in Fig. 2-4 and Fig. 2-5.

The advantages about sol-gel method are as followings [22, 23]:

1. Easy to control oxidation rate.

2. Low cost of this method compare with other oxidation process.

3. The oxidation system need not involve excessive energy.

4. Low controlled time for uniformity over on the sample rapidly.

5. Large-area oxide films obtained in this process.

The following steps of the sol-gel TiO2 procedures exhibited in below:

1. Sol-gel processed TiO2 prepared by mixed with oxide and Pentane-2, 4-dione and 2-Methoxyethanol.

2. We placed dissolved solution in the shake table to stir the solution with a stirrer bar.

3. Coating the dissolved solution on the sample which has gate recess.

4. Spinning the sol-gel processedTiO2 using spin coater for obtaining uniformly distributed thickness on the sample.

5. The final step about oxide bonding sample which is accomplished by baking the wafer in an oven.

Fig. 2-1 The mixed solution preparation.

Fig. 2-2 Spin-coating a mixed solution on the sample.

Fig. 2-3 Soft baking.

Fig. 2-4 Flow chart of the sol-gel processes.

Fig. 2-5 The oxidation of deposited the sol-gel processed TiO2 solution on InP schottky layer.

Chapter 3

Fabrication Procedures of InAlAs/InGaAs MOS-MHEMT

The gate recess using Phosphoric Acid mixture (H3PO4:H2O2:H2O) etch the block of schottky layer, which obtain the roughness surface on the InP layer further causing the surface state. For solving above problem, we offer the oxidation about solution-gelation (sol-gel) process of the high-k TiO2 material.

The sol-gel processed TiO2 as gate oxide growing on InP surface that reduce the gate leakage current.

In this study, The TiO2 solution mixed with Titanium isopropoxide (760 l) and Pentane-2, 4-dione (510 l) and 2-Methoxyethanol (3.8 ml). After preparing above mixture, and placed this solution in the shake table to stir the solution.

High-k oxidation process deposited by coating the sol-gel on the gate recessed schottky area of device and spin coated solution which attached to our samples, and then baking using oven for drying the moisture.

3.1 Device structure

The epitaxial structure of studied MHEMT was grown by metal-organic

layers, a undoped InP schottky layer, a 10nm InGaAs capping with a silicon doping density of 510¹⁸cm^-3. The cross-sectional view of the device substrate exhibited in Fig. 3-1.

3.2InAlAs/InGaAs MOS-MHEMT

The experimental processes of sol-gel processed TiO2 as gate oxide for InAlAs/InGaAs MOS-MHEMT with the gate dimensions are 100 1m²described in this section show in Figs. 3-2.The flow charts of MOS-MHEMT’s fabrication show in Figs. 3-3, 3-4 and 3-5. The related production methods of device as described below.

A. Mesa isolation

(1) In order to remove dust on the surface of the wafer, the wafers were cleaned by acetone, methanol, and DI water with ultrasonic vibration for 5 min.

(2) Coating the positive photoresist (I123) on the wafer and spin coated wafer by using spin coating at 7500 rpm for 37 s.

(3) Soft baked wafer on a hotplate at 90 ℃ for 5 min to dry the solvent in the photoresist.

(4) Mesa pattern defined by using DUV photolithograph aligner (Karlsuss MJB-3) to expose 8 s and then dip wafer in developer for 15 s to achieve development

(5) Mesa isolation defined was completed by wet etching Phosphoric Acid solution (H3PO4:H2O2:H2O = 1:1:20) to form an island region for prevent

(6) The wafer cleaned by immersing in the acetone for remove the photoresist.

B. Ohmic contact

(1) Coating the positive photoresist (I123) on the wafer and spin coated wafer by using spin coating at 7500 rpm for 37 s.

(2) Soft baked wafer on a hotplate at 90 ^℃ for 5 min to dry the solvent in the photoresist.

(3) Ohmic pattern defined using a DUV photolithograph aligner (Karlsuss MJB-3) to expose 6 s and then dip the wafer in the developer for 15 s to achieve development.

(4) Ohmic metal deposition by evaporating AuGeNi alloy on the wafer.

(5) Lift off metal by immersing in heated PG remover and then clean the wafer in the IPA solution.

(6) Annealing the metal on Rapid thermal annealing (RTA) at 370 ^℃ 50 s for forming the source-drain electrodes.

C. Gate recess and sol-gel process

(1) The sol-gel processed TiO₂mixed with Titanium isopropoxide (760 l) and Pentane-2, 4-dione (510 l) and 2-Methoxyethanol (3.8 ml) which placed in the shake table to stir the solution at last 18 hours.

(2) Gate recess accomplished by immersing the wafer in the Phosphoric Acid solution (H3PO4:H2O2:H2O = 1:1:40) to etch capping layer.

D. Gate pattern definition

(1) Coating the positive photoresist (I123) on the wafer and spin coated wafer by using spin coating at 7500 rpm for 37 s.

(2) Soft baked wafer on a hotplate at 90 ℃ for 5 min to dry the solvent in the photoresist.

(3) Gate pattern of the wafer defined by using DUV photolithograph aligner (Karlsuss MJB-3) to expose 8 s and then dip wafer in the developer for 30 s for 15 s to achieve development

(4) Gate metal deposition by evaporating gold (Au) on the oxide layer.

(5) Lift off metal by immersing in heated PG remover and then clean the wafer in the IPA solution.

(6) Fabrication of the device is completed and further measured the DC characteristics of the device.

Fig. 3-1 Device substrate of this study.

10nm n‐In^xGa^1‐xAs^(x=0.532) cap layer 5.0E+18

5nm 

i‐

In^xAl^1‐xAs^(x=0.521) schottky layer 2nm 

i‐

InP

 

schottky layer

2nm 

i‐

InxAl1‐xAs(x=0.521) schottky layer

5nm 

i‐

In^xAl^1‐xAs^(x=0.521) spacer layer 20nm i‐InxGa^1‐xAs(x=0.532) channel layer

6nm 

i‐

InxAl1‐xAs(x=0.521) spacer layer 200nm 

i‐

InxAl1‐xAs(x=0.521) buffer layer 1100nm InAlAs Metamorphic buffer 

150nm GaAs substrate 

(a) (b)

Fig. 3-2 The cross-sectional view of (a) The conventional MHEMT and (b) The MOS-MHEMT with sol-gel TiO2.

Fig. 3-3 Step of the device fabrication (A) Mesa pattern defined, (B) Mesa isolation, (C) Removing the photoresist, (D) Source-drain pattern defined.

(A) (B)

(C) (D)

Fig. 3-4 (E) Ohmic metal deposit, (F) Lift-off ohmic metal and photoresist, (G) Rapid thermal annealing, (H) Gate recess.

(E) (F)

(G) (H)

Fig. 3-5 (I) Sol-gel processed TiO2, (J) Gate pattern defined,

(I) (J)

(K) (L)

3.3Numerical Simulation Results

In this section, we focus on the simulation of gate recess MHEMT, this structure refer from, the y-axis is defined as the direction from the substrate to the gate and the x-axis is defined as the direction from the source to the drain. In this study, the numerical calculation domain is under the gate diode that indicated by red block, the base area of red block fallow the gate dimension

1 100 μm , the thickness from the gate to the channel expressed as (a1).

Fig. 3-6 The organizational chart of the conventional MHEMT.

Permittivity in vacuum ∈ 8.854 10 F/cm Permittivity in InAlAs ∈ 12.73 ∈ F/cm Electron mobility μ 6500 cm / v ∙ s

Gate width W 100 μm

Gate length L 1 μm

The drain current of the HEMT at any y position is given by

I qn v w (3-1)

The electron drift velocity v is given by

v μ ε (3-2)

Inserting Eq. (3-2) into Eq. (3-1) we obtain

I qn μ ε W (3-3)

The electron field ε is related to potentialV as

ε (3-4)

The sheet carrier density is follow the Poisson equation [23]

Table 1: The parameter of the simulated model.

The drain current is expressed as Eq. (3-6) using Eqs. (3-4) and (3-5)

I V V V μ W (3-6)

The integral of Eq. (3-6) from 0 to gate length (L) expressed by

I dx V V V μ WdV (3-7)

The integral of Eq. (3-7) is finally led to

I 2 V V V V (3-8)

When the transistor is operated at non saturation region:

0 V V

The equation of drain current density is expressed as

I = 2 V V V V ] (3-8)

When the transistor is operated at saturation region:

V V V , V V V V

The equation of drain current density is expressed as

I V V (3-9)

However, these equations of I-V curve haven’t to take non-ideal factors into consideration such as surface state and resistance effects. In addition, the thermal annealing of source/drain (S/D) metal of the simulated model which is desirable than somewhat of device fabrication, therefore the value of the drain current density will grow severely with increased gate to drain voltage and further cause breakdown of device.

In order to consider above non-ideal factors, the drain current density will be reduced by modifying some parameters of the simulated model that exhibited in below:

(1) The electron mobility has decreased from 9800cm / v ∙ s to 6500cm / v ∙ s according to surface state.

(2) The value of the saturation current density will be decreased threefold attribute to the effect on device resistance.

The results of modified drain current density can be divided into two cases and further discussing in chapter 4. The cases areas followings:

(1) The Vth is set to -0.2 V and the thickness (a1) may be gate recessed to 8nm.

(2) The Vth is set to -0.5 V and the thickness (a1) may be gate recessed to 8.5nm.

Chapter 4

The Performance of InGaAs/InAlAs MOS- MHEMT

4.1 Direct-Current Characteristics

The DC measurement of studied device including current density-voltage curve (IDS), transconductance (gm), turn-on voltage (VON), breakdown voltage (V_BR) and gate current density (I_GS) are discussed in this section.

4.1.1 Saturated Drain Current

The measured I-V curve of conventional MHEMT is exhibited in Fig. 4-1, the gate-to-source voltage (VGS) is biased from -2 V to 0.5 V in 0.5V step, the saturated drain current density is 206.9 mA/mm at V_GS = 0.5V. Fig. 4-2 shows the measured I-V curve of MOS-MHEMT, VGS is biased from -2 V to 2 V in 0.5 V step, the saturated drain current density is 307 mA/mm at V_GS = 2 V.

Above MOS-MHEMT using sol-gel processed TiO² as gate dielectric increased the maximum operation of V_GS due to high-k material between oxide film and InP interface which provide a thick barrier to decrease the leakage current.

4.1.2 Transconductance

Transconductance (gm) of the definition following below equation:

The slope in this equation obtained by different in the value of drain current density (IDS) which associated which divided by associated VGS when the drain-to-source voltage (VDS) is fixed in the saturation area [24].When the drain-to-source voltage at 1 V, the maximumg of MHEMT is 230 mS/mm and the threshold voltage (V_th) is -1.25 V. The maximum g of the MOS-MHEMT is 193mS/mm and Vth = -0.5 V.

4.1.3 The Gate Leakage Current

The measured gate current density versus the negative gate-to-source voltage of MHEMT and MOS-MHEMT with sol-gel processed TiO2 show in Fig. 4-5 and Fig. 4-6, respectively.

In this measurement, the bell-shaped behavior appear in the MHEMT but not in MOS-MHEMT, the high-k oxide decrease the impact ionization and further suppress hot electron causing in the narrow-bandgap channel.

4.1.4 The Turn-on and Breakdown Voltage

This section focused on the improved ability of DC characteristics. The measured turn-on and breakdown characteristics of conventional MHEMT and MOS-MHEMT with sol-gel processed TiO2 show in Fig. 4-7 and Fig. 4-8, respectively.

The turn-on voltage (VON) obtained at the gate current as 1mA/mm, the gate-to-source voltage sweeps from 0 V to the VON in 0.01 V step. The VTN

measured from conventional MHEMT and MOS-MHEMT are 0.5 V and 7 V, respectively.

The off-state breakdown voltage (VBR) of MHEMT and MOS-MHEMT obtained at the gate current at -0.545 mA/mm and -0.398 mA/mm, respectively.

The gate-to-source voltage sweeps from 0 V to the VBR in -0.01 V step. The VBR

measured from conventional MHEMT and MOS-MHEMT are -5 V and -40 V, respectively. The increasing VON and improved VBR in MOS-MHEMT with high-k material can be obtained from above results.

4.2Numerical Simulation Result

The two cases of modified drain current density had exhibited in section 3.3.

Fig. 4-9 shows the drain current density which has amended by case1andFig.

4-10 shows the drain current density which has amended by case 2, respectively.

However, the drain current density is still not conformed to the actual value of device fabrication. Therefore, we will adjust the current for attaining the actual value. Fig. 4-11 and Fig. 4-13 show the reduced I-V characteristics and associated gm which has adjusted from case 1, respectively. Fig. 4-12 and Fig.

4-14 show the reduced I-V characteristics and associated gm which has adjusted from case 2, respectively.

0.0 0.5 1.0 1.5 2.0 0

100 200

300 conventional MHEMT

V_GS = -2 V to 0.5 V, step = 0.5 V

W / L

= 100  ^m /1 ^m

Drain current density (mA/mm)

Drain-to-source voltage V_DS (V)

Fig. 4-1 The I-V characteristics of the conventional MHEMT.

0.0 0.5 1.0 1.5 2.0 2.5 0

100 200 300 400

MOS-MHEMT

VGS = -2 V to 2 V, step = 0.5 V

W / L

= 100  ^m /1 ^m

Drain current density (mA/mm)

Drain-to-source voltage V

DS (V)

Fig. 4-2 The I-V characteristics of the MOS-MHEMT.

-1.5 -1.0 -0.5 0.0 0.5

Gate-to-source voltage V_GS (V)

  Fig. 4-3 The drain current density and the transconductance versus gate bias voltage of the conventional MHEMT.

   

 

Drain current density (mA/mm) Transconductance (mS/mm)

Gate-to-source voltage V_GS (V)

0 100 200 300

  Fig. 4-4 The drain current density and the transconductance versus gate bias voltage of the MOS-MHEMT.

   

VDS = 2 V

Fig. 4-5 The gate current density versus reverse gate voltage of the conventional MHEMT at VDS= 2 V, 2.25 V and 2.5 V.

-2.4 -2.0 -1.6 -1.2 -0.8 -0.4 0.0 -0.050

-0.045 -0.040 -0.035 -0.030 -0.025 -0.020 -0.015

V_DS = 2 V V_DS = 2.2 V V_DS = 2.4 V W/L = 100  ^m/1 ^m MOS-MHEMT

Gate current density (mA/mm)

Gate-to-source voltage V_GS (V)

Fig. 4-6 The gate current density versus reverse gate voltage of the MOS-MHEMT at VDS= 2 V, 2.2 V and 2.4 V.

0 1 2 3 4 5 6 7 8 0.0

0.2 0.4 0.6 0.8 1.0

MOS-MHEMT

conventional MHEMT W/L = 100  ^m /1 ^m

Gate current density (mA/mm)

Gate-to-drain voltage V_GD(V)

Fig. 4-7 The turn-on voltage of MOS-MHEMT compared with conventional MHEMT.

-45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 1E-5

1E-4 1E-3 0.01 0.1 1

MOS-MHEMT

conventional MHEMT W/L = 100 ^m /1 ^m

Gate current density (mA/mm)

Gate-to-drain voltage V

GD (V)

Fig. 4-8 The off-state breakdown voltage of MOS-MHEMT compared with conventional MHEMT.

 

Table 2: DC characteristics of measurement for different devices in this work.

MHEMT MOS-MHEMT

I  

mA/mm 206.9 307

gm  

(mS/mm) 230 193

Vt h (V) -0.5 -1.3

Vo n (V) 0.5 7

VB R (V) -5 -40

0.0 0.5 1.0 1.5 2.0

Fig. 4-9 The I-V characteristics which is amended by case 1.

0.0 0.5 1.0 1.5 2.0

Drain-to-source voltage V_DS (V)

Fig. 4-10 The I-V characteristics which is amended by case 2.

0.0 0.5 1.0 1.5 2.0 0

100 200 300

conventional MHEMT

VGS = -0.2 V to 0.7 V, step = 0.1 V W / L

= ¹⁰⁰  ^m /1 ^m

Drain current density (mA/mm)

Drain-to-source voltage V

DS (V)

Fig. 4-11 The reduced I-V characteristics associated with Fig. 4-9.

0.0 0.5 1.0 1.5 2.0 0

100 200 300 400

conventional MHEMT

VGS = -0.5 V to 0.5 V, step = 0.1 V W / L

= ¹⁰⁰ ^m /1 ^m

Drain current density (mA/mm)

Drain-to-source voltage V_DS (V)

Fig. 4-12 The reduced I-V characteristics associated with Fig. 4-10.

-0.70 -0.35 0.00 0.35 0.70 0

100 200 300

Gate-to-source voltage V_GS (V) conventional MHEMT

VDS = 1 V W / L

= 100 ^m /1 ^m

Drain current density (mA/mm) Transconductance (mS/mm)

0

Fig. 4-13 The transconductance associated with Fig. 4-11.

-1.0 -0.5 0.0 0.5

Gate-to-source voltage V_GS (V)

Fig. 4-14 The transconductance associated with Fig. 4-12.

Chapter 5

Conclusion and future works

5.1 Conclusions

The InGaAs/InAlAs MOS-MHEMT using sol-gel processed TiO2 as gate dielectric in this thesis exhibited excellent DC characteristics compared with gate recessed HEMT, such as higher maximum drain current density widely rang of voltage operation, larger breakdown character, better turn-on voltage and reduced gate leakage current density.

MOS-MHEMT with high-k gate insulator contributed to enhance the maximum current density and also obtain a decreased surface state to suppress the impact ionization effect from the InGaAs channel layer. Therefore, the high permittivity gate insulator deposited on InP surface using sol-gel process that is suitable for power application.

5.2 Future Works

The sol-gel process after passivation treatment on schottky surface of MOS-MHEMT somewhat could be considered a promising procedure for

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