Chap 1 Introduction
1.3 Organization of this thesis
This thesis is divided into six chapters.
In Chapter 1, we have summarized the issues of pMOSFETs such as hot-carrier effects,
boron penetrations, dielectric integrity and reliability issues etc. Then we compare the
motivation of our studies.
In Chapter 2, we will describe the device structure and fabricating steps of pMOSFETs
and list the process flow and split table.
In Chapter 3, we demonstrate the characteristics of fluorine and nitrogen on pMOSFETs.
The result indicates that implantation of fluorine on substrate enhances channel
transconductance and the nitrogen in source/drain reduces short channel effect.
In Chapter 4, negative-bias-temperature instability will be discussed with different
nitrogen and fluorine implantation dosages. As we expected, the nitrogen in source/drain will
aggravate the threshold voltage shifts.
In Chapter 5, we investigate dynamic NBTI (DNBTI) on p-channel MOSFETs with
different conditions. The results show the similar trend as those in Chapter 4.
In Chapter 6, we give a brief conclusion to this study, dissertation and suggest with
future work on this topic.
Chap 2
Device fabrication
2.1 Introduction
In this chapter, we will introduce the fabrication process of p-channel MOSFETs briefly.
The p-channel MOSFETs were fabricated on 6-inch p type (100) silicon substrate with 2.5nm
gate oxide in the Nation Nano Device Laboratories (NDL). The fundamental conditions were
illustrated in Fig. 2-1 and Table 2-1
2.2 The sketch of device fabrication
First, phosphorous was implanted into the (100) Si substrates through a 35 nm sacrificial oxide at 120 keV to the dose of 1.2 × 1013/cm2. Standard LOCOS process was used for
device isolation. Fluorine was implanted into Si substrate followed by the condition as shown
in the split Table 2-1. Threshold voltage adjustment was formed by arsenic implantation at 80
keV with the 1.2 × 1013/cm2 dosage and phosphorus implantation at 120 keV with the 4 ×
1012/cm2 dosage in order to anti-punch through.
After the RCA cleaning process, 2.5 nm gate oxide was grown in a vertical furnace with
O2 at 800 °C. A 200 nm poly-Silicon was deposited at 600 °C after gate oxidation. Fluorine
and/or nitrogen was implanted into the poly-silicon gate followed the condition as shown in
the split table. Dry etcher, TCP-9400 Lam Research, was used to etching poly-silicon gate
after behind gate patterning process. The sidewall spacer was formed by a conformal
deposition of 200 nm TEOS oxide and a subsequent reactive ion etching (RIE). Then,
Fluorine and/or nitrogen was implanted again under the split conditions as shown in the split
table before S/D extension implantation. The self-alignment process was used to form source
and drain electrode by implanting BF2 at 10 keV with the dose of 5 × 1012/cm2.
Substrate etching and substrate implantation were executed continuously. Rapid thermal
annealing (RTA) was performed at 1000 °C for 10 seconds to activate the dopants and
annealed out the damage from ion-implantation. The passivation layer was deposited by
TEOS at 700 °C for 550 nm. After contact etching, four-layer metal (Ti / TiN / Al / TiN) were
carried out in a PVD system. Finally, wafers were annealed in forming gas (H2 / N2) ambient
at 400 ℃ for 30 minutes.
2.3 Device fabrication process flow
【1】N-Well implantation
1. HF dip for 1 minute
2. Deposition of sacrificial oxides with the thickness of 35nm at 925 °C
3. N-Well Implantation with the dose of 1.2 × 1013 /cm2 at 120 keV
4. Well drive-in at 1100 °C
5. BOE for 3 minutes
【2】LOCOS Definition
1. Deposition of pad oxide with the thickness of 35nm at 925 °C
2. Deposition of Si3N4 with the thickness of 150nm at 780 °C
3. LOCOS alignment (Mask 2 AA-I)
4. Use RIE (TEL5000) to etch Si3N4
5. N-field implantation with the dose of 2 × 1013 /cm2 at 120 keV
6. P.R. stripping
7. Formation of field oxide with the thickness of 550nm at 980 °C
8. BOE dip for 15 seconds
9. Remove Si3N4 layer
【3】Vth adjustmentImplantation:
1. HF for 8 minutes
2. Formation of sacrificial oxide with the thickness of 30nm at 925 °C
3. HF dip for 8 minutes
4. Formation of sacrificial oxide with the thickness of 30nm at 925 °C
5. Implantation conditions were followed by split table
6. As+ ion implantation with the dose of 1.2 × 1013 /cm2 at 80 keV
7. P-APT implantation with the dose of 4 × 1012 /cm2 at 120 keV
【4】Gate pattern definition:
1. HF for 8 minutes
2. RCA Clean
3. HF dip for 1 minute
4. 25nm O2oxidation in vertical furnace
5. 200nm poly-Si deposition at 625 °C
6. Implantation conditions were followed by split table
7. Gate Alignment (Mask 3 POLY-I)
8. Poly-Silicon etching by TCP-9400
9. P.R. stripping
【5】S/D formation:
1. Implantation conditions were followed by split table
2. BF2 implantation with the dose of 1 × 1015 /cm2 at 5 keV for S/D extension
3. Growth of 200nm TEOS oxides at 700 °C
4. Dry etching of TEOS oxides by TEL5000
5. BF2 implantation with the dose of 5 × 1015 /cm2 at 10 keV for S/D implantation
6. N+ substrate alignment (MASK 5 SUBSTRATE OPENING-I)
7. Sub-etching by TEL5000
8. N+ substrate implantation with the dose of 5 × 1015 /cm2 at 40 keV
9. P.R. Stripping
10. Activation at 1000 °C for 10 seconds.
【6】Contact holes formation:
1. Deposition of 550nm TEOS oxides
2. Contact alignment (Mask 6 Contact-1)
3. Use TEL5000 and BOE to etch contact hole
4. Remove P.R.
【7】Metallization:
1. HF dip for 2 minutes
2. Sputter 40 / 100nm Ti / TiN films
3. Sputter 900nm Al-Si-Cu films
4. Metal alignment (Mask 7 PAD-I)
5. Metal etching by ILD-4100
6. P.R. Stripping
7. Post-metal annealing (PMA) at 400 °C for 30 minutes in H2 / N2 ambient
Chap 3
Device Measurement and Characteristics
3.1 Introduction
In this chapter, I-V characteristics of pMOSFETs with 2.5-nm gate oxide thickness were
characterized in detail. The methods of measurement are briefly also described. Transistor
characteristics depend on the location of fluorine and nitrogen. We will explain the resultant
difference in pMOSFETs with fluorine and nitrogen incorporation.
3.2 Methods of Device Parameter Extraction
The transistor performance and I-V characteristics of the pMOSFETs were measured
using a KEITHLEY 4200 semiconductor parameter analyzer with source and bulk grounded.
In the nonsaturation region, we will obtain the ideal drain current for p-channel MOSFET
)
and, in the saturation region, we will have
)
inversion layer, COX is the oxide capacitance per unit area, VSG is the source-to-gate voltage,
and VSD is the source-to-drain voltage.
The MOSFET transconductance is defined as the change in drain current with respect to
the corresponding change in gate voltage for linear region：
)
subthreshold currents and above VT due to series resistance and mobility degradation effects.
It is common practice to find the point of maximum slope on the ID-VGS curve by a maximum in the transconductance,
GS
We use a charge pumping technique to investigate interface-state densities in pMOSFETs.
This method is suitable for interface trap measurements on small-geometry MOSFETs instead
of large-diameter MOS capacitors. Figure 3-1 illustrates a basic setup for charge-pumping
measurements. The MOSFET source and drain are tied together and reverse-biased with a
voltage VR. The time-varying gate voltage is of sufficient amplitude for the surface under the
gate to be driven into inversion and accumulation. The pulse train can be square, triangular etc.
Here we use square and triangular waveforms generated by an Agilent 81110 pulse generator.
The charge pumping currents are measured at the substrate, with source and drain tied
together. When a p-MOSFET channel is pulsed into inversion, hole currents from source/drain
can flow into the channel, where some of the holes will be captured by the surface states.
When the gate pulse is driving the surface back to accumulation, the hole charges drift back to
the source and drain, but those hole charges trapped in the surface states will recombine with
the electrons from the substrate and give rise to a net flow of negative charges into the
substrate. This substrate current can be directly related to the surface-state density.
3.3 Results and Discussion
First, we determined some notations to represent our spilt conditions. “B” is represented
“Bulk”, “S/D” is represented “source and drain”, “G” is represented “Gate”, “B(F)” means
that the fluorine is implanted into bulk Si at 15 keV with the 1 × 1014/cm2 dosage, and
“S/D(N)” is represented that the nitrogen is implanted into source/drain at 15 keV with the 1
× 1014/cm2, and “S/D(N*)” is represented that the nitrogen is implanted into source/drain at
15 keV with the 1 × 1015/cm2.
In this section, we would introduce the nitrogen and fluorine effects on different
positions of pMOSFETs with different dosages. In Fig. 3-2, we measured different
dimensions of devices. We found that incorporation of nitrogen into poly-Si gate with the
dose of 1 × 1015/cm2 have large threshold voltage. On the contrary, gate implanted fluorine
reduced threshold voltage. This is because that fluorine in the poly-Si gate will enhance boron
diffusion through gate oxide into substrate and nitrogen will retard boron diffusion into bulk
silicon. Figure 3-3 illustrate the effect of nitrogen incorporation into source/drain junction. In
the annealing process, nitrogen will decrease boron out-diffusion from source/drain extension
region. Therefore, this implantation condition reduced threshold voltage roll off effects.
We measured ten devices for each split condition to extract the average transconductance
and threshold voltage. Figure 3-4 and Figure 3-5 depict that fluorine in the substrate will
enhance the transconductance at the same condition. As a result, this may be due to the
improvement at the interface when F is incorporated. The charge-pumping current is
measured for these devices. We found it is not the case as we expected. In Figure 3-6, the Icp
of device with fluorine implanted substrate exhibits a larger Icp current. Figure 3-7 illustrates
source/drain sheet resistance for different implantations at poly-silicon gate and bulk-Si. We
found that sheet resistance in source/drain region dominate transconductance degradation
phenomenon. Nitrogen incorporation into gate with the dose of 1 × 1014/cm2 will also
enhance the transconductance. But large nitrogen concentration reduces the transconductance.
This is due to the combination of N-B in the gate, causing the poly-depletion effect. This
makes the effective oxide capacitance decrease. Threshold voltage characteristics with
different poly-gate and bulk-Si implantation of pMOSFETs characteristics are shown in Fig.
3-8 and Fig 3-9. Fluorine in the substrate results in a small threshold voltage and nitrogen in
the gate has large threshold voltage. Because fluorine was implantated all over the active
region including source/drain junction, the following annealing process will let fluorine
enhance boron diffusion into the channel region. Implanting nitrogen with the dose of 1 ×
1015/cm2 increased the threshold voltage due to poly depletion effect, which causes the
decrease of oxide capacitances.
Figure 3-10 and Figure 3-11 shows the transconductance with different source/drain and
bulk-Si implantation. We found that nitrogen implantation into source/drain decreased
transconductance. Devices with fluorine in source/drain has large transconductance than
nitrogen ones. This may be due to the diffusion of nitrogen toward silicon/oxide interface
during annealing process and cause interface state as shown in Fig.3-12. Moreover, sheet
resistance in source/drain region also affects the transconductance. In Fig 3-13, we found that
fluorine in source/drain has large sheet resistance than nitrogen in source/drain. In Fig. 3-14
and Fig. 3-15, nitrogen in source/drain has large threshold voltage due to prevention of boron
diffusion by nitrogens. Fluorine incorporation into source/drain has small threshold voltage
than nitrogen incorporation into source/drain. Since fluorine enhance boron diffusion to bring
small threshold voltage.
To compare fluorine incorporation into poly-silicon gate with silicon substrate, we have
some results as shown in Fig. 3-16 and Fig. 3-17. Fluorine in poly-silicon gate reduce
transconductance. Figure 3-18 and Figure 3-19 show that fluorine implantation into gate
results the reduction of threshold voltage. It is known that pile-up of fluorine from the fluorine
and/or BF2 gate implant at the poly-silicon/gate oxide interface is responsible for the
enhanced boron penetration.
3.4 Summary
In this chapter, electrical characteristics of fluorine and nitrogen effects on pMOSFETs
were measured in detail. First, we find that large nitrogen concentration in poly-silicon gate
results in poly-depletion effect and possess larger threshold voltage. Second, nitrogen in
source/drain extension region has a better immunity to threshold voltage roll-off phenomenon.
On the other hand, fluorine incorporation into silicon substrate enhances the transconductance,
which is similar to nitrogen incorporation into poly-silicon gate. The implantation of nitrogen
into poly-Si gate can effectively suppress the boron penetration deleterious to pMOSFET with
thin gate oxide. But we found that this implantation will increase interface state density.
Finally, we have also shown that fluorine in poly-Si gate can reduce the transconductance.
Therefore, boron penetration, poly-depletion and threshold voltage effects are combinational
issue while we try to enhance devices’ performance by incorporating nitrogen and fluorine
into pMOSFETs.
Chap4
Negative bias temperature instability of pMOSFETs with different nitrogen and fluorine implantation dosages
4.1 Introduction
Generation of interface traps during negative bias temperature instability (NBTI) stress
in p+-gate pMOSFETs has been the most critical issue for the reliability as continuous scaling
down of ULSI devices. Moreover, it has been reported that NBT degradation of oxynitride
dielectrics (SiON) is remarkably enhanced. On the contrary, the addition of fluorine into gate
oxide improved negative bias threshold instability. In this chapter, we investigated the NBTI
effects on pMOSFETs with the different dosages of nitrogen and fluorine incorporation. The
devices were applied to the gate electrode of pMOSFET at high temperatures with
source/drain grounded and the stress condition is under Vg = -3.5 V at 150°C shown in Fig.
4-1.
4.2 Researches about the mechanisms of NBTI
During negative bias temperature instability stress, the interface states Nit, trivalent silicon dangling bonds Si3 ≡ Si•, and fixed oxide charges (O3 ≡ Si−) are generated by the
impact of hot holes on the hydrogen-terminated Si bonds and contribute to the negative
threshold voltage shift [44],[45]. The electrochemical reactions are expressed as follows:
The holes are activated thermally and gain enough energy to dissociate the
interface/oxide defects by the vertical electrical field near the LDD regions because of higher
hole concentrations near the gate edge. Initially, the reaction favors the generation of interface
states and produces hydrogen atoms and ions at the interface. And this process is limited by
the dissociation rate of hydrogen-terminated Si bonds. After some stress time, however, the
transport of hydrogen ions in the oxide dominates and its diffusion rate is controlled by two
factors: (a) the modified oxide field due to the existing hole trapping in the oxide and the
formation of positive fixed oxide charges. (b) the gradually increasing interface states
≡ Si•
Si3 . Hence, further diffusion of protons or the generation of interface states will be discouraged. When reaction (4.1) reaches the balanced condition, the main electrochemical
reaction becomes the diffusion of neutral hydrogen atoms in (4.2) and (4.3).
4.3 Results and Discussion
In this section, we employ charge pumping methods to extract interface-trap density [46].
At high frequencies, the Icp current is given by
)
We use two kinds of pulse train as square and triangular. The first form obtain
interface-trap densities near conduction band and valance band, the latter form obtain
interface-trap densities close to deeper level. By using this method, we can realize different
levels of interface-trap density.
Figure 4.2 shows threshold voltage shift under NBTI stress with different source/drain
and bulk-Si implantation. The BT stress condition is Vg = - 3.8 V at 150°C. We found an
interesting result. Although higher nitrogen implantation at source/drain extension region
reduces short channel effect, it decreases device reliability under NBTI stress. It can be
explained by the locally enhanced degradation reactions between holes and oxide near the
source/drain extension region, and the nitrogen may diffuse toward the silicon/oxide interface
during RTA processing step or lateral scattering of ion implantation. In Fig. 4-3, interface-trap
density of nitrogen implantation at source/drain extension region has the maximal Nit than
others. Triangle wave has the same trend as shown in Fig. 4-4. There is another reason for
nitrogen reduce reliability phenomenon. Fig. 4-5 shows temperature dependence of NBTI
stress. In the figure, slope is proportional to active energy. So, nitrogen cause lower Ea let
device owning poor reliability.
Figure 4-6 shows threshold voltage shift under NBTI stress for pMOSFETs with
different source/drain implantation. Fluorine incorporation into source/drain extension region
has a better reliability than nitrogen does. Figure 4-7 and Figure 4-8 exhibit the account for
this result. In the annealing process, nitrogen diffusion to Si/SiO2 interface causes an increase
of interface-trap density than fluorine influence does. The result is corresponding to Fig. 3-12
as we expected. Threshold voltage shift under NBTI stress for different poly-silicon gate and
bulk-Si implantation as shown in Fig. 4-9. In chapter 3, we have known that fluorine
implantation into silicon substrate has more interface-trap density opposite to control wafer
(compare to Fig. 3-6). This figure suggests fluorine and nitrogen incorporation into
poly-silicon gate enhance device reliability and nitrogen implantation has the better efficiency
than fluorine. Maybe it is related to fluorine enhances boron diffusion through gate insulator
into silicon substrate. We also found the similar result as shown in Fig 4-10. Besides, we
investigate difference poly-silicon gate implantation without substrate implantation. In Fig.
4-11, nitrogen and fluorine implantation into gate can also increase reliability issues. Nitrogen
incorporation into poly-silicon gate with the 1 × 1015/cm2 dosage has the better immunity for
NBTI stress than fluorine incorporation into poly-silicon gate with the 1 × 1014/cm2 dosage.
Figure 4-12 illustrates interface state for the same condition as that in Fig. 4-10. Moreover, it
shows the similar result as before.
4.4 Summary
NBTI effects on pMOSFETs with the different dosages of nitrogen and fluorine
incorporation were investigated in this chapter. Although nitrogen at the source/drain
extension region can reduce threshold voltage roll-off effects, however, nitrogen diffusion
from source/drain extension region into channel interface during RTA processing step makes
the NBTI of pMOSFETs more serious. Therefore, the implantation must be trade-off for
devices’ fabrication. We found that the method of nitrogen and fluorine implantation into
poly-silicon gate can be used to enhance device reliability performance.
Chap 5
Dynamic Negative bias temperature instability of pMOSFETs with different nitrogen and fluorine
implantation dosages
5.1 Introduction
In conventional NBTI study, a constant negative bias is applied to the gate electrode as
the “high” output state in a CMOS inverter. However, the applied gate bias is switching
between “high” and “low” voltage during the operation of pMOSFETs in CMOS inverters,
while the drain bias is alternating between “low” and “high” voltage correspondingly. During
low output phase of an inverter, the electric passivation (EP) effect reduces the interface traps
generated during high output phase effectively and recovers the degradations of device
parameters for a certain degree. This “Dynamic” negative bias temperature instability
(DNBTI) operating in a CMOS inverter circuit prolongs the device lifetime significantly.
Therefore, it is important to investigate dynamic stress conditions. In this chapter, we clarified
the DNBTI effects to our splits. The positive gate voltages were stressed under Vg = 0 V at
150°C.
5.2 Researches about the mechanisms of DNBTI
The passivation effect or dynamic NBIT can be explained by extending the previous
Hydrogen diffusion–reaction model [47]–[50]. The interface trap generation is ascribed to hydrogen release from a hydrogen terminated silicon-dangling bond (Si≡Si−H ), first
proposed by Balk in 1965. Under high-temperature and negative gate bias stress conditions,
the holes from the induced inversion layer react with the interface trap precursors (Si≡Si−H ), breaking the H–Si bond and resulting in interface traps Nit (Si dangling bonds).
The produced hydrogen-related species, denoted as X in Fig. 5-1(a), diffuse/drift to the gate
electrode. During this stress period, the interface acts as a hydrogen source. The electric
passivation (EP) effect can be readily interpreted by the reverse reaction between Nit and X
passivation (EP) effect can be readily interpreted by the reverse reaction between Nit and X