1.1 General Background
1.1.1 Overview of Poly-Silicon thin-film transistors
In recent years, polycrystalline silicon thin-film transistors (poly-Si TFTs) have drawn
much attention because of their widely applications on active matrix liquid crystal displays
(AMLCDs) [1], and organic light-emitting displays (OLEDs) [2]. Except large area displays,
poly-Si TFTs also have been applied into some memory devices such as dynamic random
access memories (DRAMs) [3], static random access memories (SRAMs) [4], electrical
programming read only memories (EPROM) [5], electrical erasable programming read only
memories (EEPROMs) [6], linear image sensors [7], thermal printer heads [8], photo-detector
amplifier [9], scanner [10], neutral networks [10]. Lately, some superior performances of
poly-Si TFTs also have been reported by scaling down device dimension or utilizing novel
crystallization technologies to enhance poly-Si film quality [11-12]. This provides the
opportunity of using poly-Si TFTs into three-dimension (3-D) integrated circuit fabrication.
Of course, the application in AMLCDs is the primary trend, leading to rapid developing of
poly-Si TFT technology. The major attraction of applying polycrystalline silicon thin-film
transistors (poly-Si TFTs) in active matrix liquid crystal display (AMLCDs) lies in the greatly
elements and the capability to integrate panel array and peripheral driving circuit on the same
substrates [13-15]. In poly-Si film, carrier mobility larger than 15 cm2/Vs can be easily
achieved, that is enough to used as peripheral driving circuit including n- and p-channel
devices. This enables the fabrication of peripheral circuit and TFT array on the same glass
substrate, bring the era of system-on-glass (SOG) technology. The process complexity can be
greatly simplified to lower the cost. In addition, the mobility of poly-Si TFTs is much better
than that of amorphous ones, the dimension of the poly-Si TFTs can be made smaller
compared to that of amorphous Si TFTs for high density、high resolution AMLCDs, and the
aperture ratio in TFT array can be significantly improved by using poly-Si TFTs as pixel
switching elements. This is because that the device channel width can be scaled down while
meeting the same pixel driving requirements as in α-Si TFT AMLCDs. For making high
performance poly-crystalline silicon (poly-Si) thin film transistors (TFTs) [16],
low-temperature technology is required for the realization of commercial flat-panel displays
(FPD) on inexpensive glass substrate, since the maximum process temperature is limited to
less than 600℃. There three major low-temperature amorphous-Si crystallization methods to
achieve high performance poly-Si thin film, solid phase crystallization (SPC), excimer laser
crystallization (ELC), and Metal-Induced Lateral Crystallization (MILC) However, some
problems still exist in applying poly-Si TFTs on large-area displays. In comparison with
single-crystalline silicon, poly-Si is rich in grain boundary defects as well as intra-grain
defects, and the electrical activity of the charge-trapping centers profoundly affects the
electrical characteristics of poly-Si TFTs. Large amount of defects serving as trap states locate
in the disordered grain boundary regions to degrade the ON current seriously [17]. Moreover,
the relatively large leakage current is one of the most important issues of conventional poly-Si
TFTs under OFF-state operation [18-19]. In most application, a low-cost substrate is essential
and therefore a low temperature process (i.e., <650°C) compatible with glass 2 substrates is
developed [20]. In summary, it is expected that the poly-Si TFTs will becomes more
important in future technologies, especially when the 3-D circuit integration era is coming.
More researches studying the related new technologies and the underlying mechanisms in
poly-Si devices with shrinking dimensions are therefore worthy to be indulged in.
1.1.2 Defects in Poly-Si film
Due to the granular structure of the poly-Si film, a lot of grain boundaries and intragranular
defects exist in the film. The dangling bonds in grain boundaries will affect device
characteristics seriously because they act as trapping centers to trap carriers. Carriers trapped
by these low energy traps can no longer contribute to conduction, which results in the
formation of local depletion region and potential barriers in these grain boundaries. Thus, the
typical characteristics such as threshold voltage, subthreshold swing, ON current, mobility
and transconductance of TFTs are inferior to those of devices fabricated on single crystal
silicon film. As for the leakage current, it is well known that the leakage current increase with
the drain voltage and gate voltage. The dominant mechanism of the leakage current is field
emission via grain boundary traps due to the high electric field near the drain junction [21-24].
To overcome this inherent disadvantage of poly-Si film, many researches have been focused
on modifying or eliminating these grain boundary traps. Traps are associated with dangling
bonds arising from lattice discontinuities between different oriented grains or at the Si/SiO2
interface. The most useful method so far to remove traps is to passivate these dangling bonds,
such as hydrogen plasma treatment has been utilized for the passivation [25-26], but it is
difficult to control the hydrogen concentration in the TFT. The Si-H bonds may be broken
under hot-carrier stress [27-28], leading to degradation of electrical characteristics after a
long-term operation time. As the number of trapped carrier decreases, the potential barriers in
grain boundaries decrease. And the leakage current decreases because of the fewer trap
density near the drain region.
1.1.3 Transport properties of Poly-Si
As mentioned in section 1.1.1 and 1.1.2, the device characteristics of poly-Si TFTs are
strongly influenced by the grain structure in poly-Si film. Even though the inversion channel
region is also induced by the gate voltage as in MOSFETs, the existence of grain structure in
channel layer bring large differences in carrier transport phenomenon. Many researches
studying the electrical properties and the carrier transport in poly-Si TFTs have been reported.
A simple grain boundary-trapping model has been described by many authors in details
[29-31]. In this model, it is assumed that the poly-Si material is composed of a linear chain of
identical crystallite having a grain size Lg and the grain boundary trap density Nt. The charge
trapped at grain boundaries is compensated by oppositely charged depletion regions
surrounding the grain boundaries. It is shown in Figure. 1-1. From Poisson’s equation, the
charge in the depletion regions causes curvature in the energy bands, leading to potential
barriers that impede the movement of any remaining free carriers from one grain to another.
When the dopant/carrier density n is small, the poly-Si grains will be fully depleted. The
width of the grain boundary depletion region xd extends to be Lg/2 on each side of the
boundary, and the barrier height VB can be expressed as
s
As the dopant/carrier concentration is increased, more carriers are trapped at the grain
boundary. The curvature of the energy band and the height of potential barrier increase,
making carrier transport form one grain to another more difficult. When the dopant/carrier
density increases to exceed a critical value N* = Nt / Lg, the poly-Si grains turn to be partially
depleted and excess free carriers start to spear inside the grain region. The depletion width
and the barrier height can be expressed as
n
The depletion width and the barrier height turn to decrease with increasing dopant/carrier
density, leading to improved conductivity in carrier transport. The carrier transport in fully
depleted poly-Si film can be described by the thermionic emission over the barrier. Its’
current density can be written as [32].
)]
barrier height without applied bias, and Vg is the applied bias across the grain 8
boundary region. For small applied biases, the applied voltage divided approximately
uniformly between the two sides of a grain boundary. Therefore, the barrier in the
forward-bias direction decreases by an amount of Vg/2. In the reserve-bias direction, the
barrier increases by the same amount. The current density in these two directions then can be
expressed as
the net current density is then given by
2 )
at low applied voltages, the voltage drop across a grain boundary is small compared to the
thermal voltage kT/q, Eq. (1.7) then can be simplified as
)]
the average conductivity σ = J / Ε = JLg / Vg and the effective mobility μeff = σ / qn
where μ0 represents the carrier mobility inside grain regions. It is found that the conduction
in poly-Si is an activated process with activation energy of approximately qVB, which depends
on the dopant/carrier concentration and the grain boundary trap density. Applying gradual
channel approximation to poly-Si TFTs, which assumes that the variation of the electric field
in the y-direction (along the channel) is much less than the corresponding variation in the
z-direction (perpendicular to the channel), as shown Fig. 1-2. The carrier density n per unit
area (cm-2) induced by the gate voltage can be expressed as
ch
where tch is the thickness of the inversion layer. Therefore, the drain current ID of poly-Si TFT
then can be given by
Obviously, this I-V characteristic is very similar to that in MOSFETs, except that the mobility
is modified.
1.1.4 Non-ideal effect
There are two major non-ideal effects will limit the TFTs application, including leakage
current and kink-effect. The mechanism of these two non-ideal effects is described briefly as
bellow.
1.1.4.1. Leakage current
In AMLCD, TFTs play a switching device to turn ON/OFF the current path for
charging/discharging the liquid crystal capacitor. Thus, the leakage current should be low
enough to remain a pixel gray level before it must be refreshed. The leakage current
mechanism in poly-Si has been studied by Olasupe [33]. The leakage current resulted from
carrier generation from the poly-Si grain boundary defects. There are three major leakage
mechanisms, as shown in Fig. 1-3. The dominant mechanism is a function of the prevailing
drain bias. They pointed out carrier generation from grain boundary defects via thermionic
emission and thermionic field emission to be prevalent at a low and medium drain biases, and
carrier pure tunneling from poly-Si grain boundary defects to be the dominant mechanism at
higher drain bias.
1.1.4.2. Kink effect[34]
During devices operation, a high field near the drain could induce impact ionization there.
Majority carriers, holes in the p-substrate for an n-channel poly-Si TFTs, generated by impact
ionization will be stored in the substrate, since there is no substrate contact to drain away
these charges. Therefore the substrate potential will be changed and will result in a reduction
of the threshold voltage. This, in turn, may cause an increase or a kink in the current-voltage
characteristics. The kink phenomenon is shown in Fig. 1-4. This float-body or kink effect is
especially dramatic for n-channel devices, because of the higher impact-ionization rate of
electrons. The kink effect can be eliminated by forming a substrate contact to the source of the
transistor.
1-2. Motivation
Low-temperature polycrystalline silicon thin film transistors (LTPS TFTs) have attracted
much attention due to the possibility of realizing the integration of driving circuits and pixel
elements on one substrate，and the potential to accomplish the system-on-panel(SOP)。To
meet the requirement of higher circuit density and higher speed, it is necessary to improve the
performance of the poly-Si TFTs. However, it has been shown that the performances of
poly-Si are affected by the trap states at grain boundaries. In the preview research, Enlarging
the grain size and passivating the defects at the grain boundary were widely used methods to
reduce the trap states in the grain boundary. Generally, hydrogen plasma treatment has been
utilized for the passivation, but it is difficult to control the hydrogen concentration in the
TFTs. In recent years, fluorine and nitrogen ion implantation was applied to improve the
electrical characteristics by eliminating the defects in the grain boundary [35-37].However
large off-state leakage current and poor stability of polycrystalline silicon thin film transistors
(poly-Si TFTs) fabricated by excimer laser annealing(ELA) due to high trap states in poly-Si
grain boundaries and at the interface between poly-Si channel layer and gate dielectric are still
serious problems。Recently it has been reported that residual ion implantation damage at
source/drain junctions of ELA poly-Si TFTs entitled “junction defect” shown in Fig. 1-5
[38]is also one of the problems of poly-Si TFTs。In order to eliminate the junction defects，
we propose a poly-Si defect passivation technique wherein the passivating species (Fluorine
and Nitrogen) is introduced via ion implantation into the source/drain region。In addition，
doses of fluorine and nitrogen varying from 1x1014 to 1x1015 cm-2 were implanted in this
work。The electrical characteristics, including I-V measurement , were reported in this study.
1.3 Thesis Organization Chapter 1 Introduction
1.1 General Background
1.1.1 Overview of Poly-Silicon thin-film transistors