Chapter 4 Segment Tree
4.2 Tree Operation
4.2.3 p-node Fetching
Both point-to-component and component-to-component routing require fetching the p-node of tree to initial the routing process. This operation is implemented by storing the pointers of all s-nodes of an S-tree in a linked list. Another memory-efficient method is to store the pointers of all leaf s-nodes of a tree in a linked list, the S-tree can traversed by starting traverse at each leaf s-node.
Chapter 5
Experimental Results
We implemented our tile-based router in this work using the C++ language on the 1.2GHz SUN Blade 2000 workstation with 2GB memory. We compare our tile-based router to multilevel framework [21,22] with six benchmark circuits provided by the authors. Table 5.1 indicates the information of these six circuits;
include the circuit dimensions, design rules, number of routing layers, total of 2-terminal nets and the number of terminals.
Table 5.2 shows the comparisons on wire length, the number of via, run-time and the completion rate. The results show that our approach could achieve average 4.7X and 7.2X faster routing speed than [21] and [22]. The S-tree for multi-terminal routing also brings better wire length and number of via than others by about 3% to 10%.
Table 5.2. Routing results comparison.
S13207 1.9.e8 15832 115.4 99.83% 2.2e8 14938 106.7 100% 1.8e8 14185 20.42 100%
S15850 2.3.e8 18778 154.6 99.88% 2.4e8 17334 538.8 100% 2.2e8 16900 42.65 100%
S38417 5.0e8 45620 567.6 99.80% 5.9e8 43551 899.9 100% 5.0e8 41376 111.59 100%
S38584 7.0e8 63205 1308.2 99.84% 7.7e8 61053 1953.7 100% 6.9e8 56233 379.11 100%
Avg. 3.0% 10.5% 4.7X 10.5% 7.3% 7.2X
In Table 5.3, we compare the tile-based router with and without RTR at the detailed routing stage. However, the results indicate that the routing time almost is not improved, instead getting worse. It produced a contrary to our intention. It is interesting to note that if the tile plane is more fragmented the redundant tiles removal could produce the better reduction result. Besides, the time for determining the over-fragmented tile planes and performing RTR would increase the total of runtime.
The reduced rate denoted in the final column of Table 5.3 shows that these six circuits
are too sparse to reduce the redundant tiles and speedup the routing process.
The operation time spent on S-tree and Quad-tree are list in Table 5.4. In the table, the second and fifth column indicates the time for updating S-tree and quad-tree that includes the insertion and deletion time. In third column, “Query” shows the time to fetch p-node of S-tree for initial routing. The “per. routing” in the fourth and final column represents the proportion of tree operation to the total of routing time. These
auxiliary data structure provide the quick operation for the routing process with the small portion of the penalty. Figure 5.1 shows the routing result of circuit S5378.
Table 5.3 Apply Redundant Tiles Removal
Without RTR With RTR
Table 5.4. The operation time spent on S-tree and quad-tree.
S-tree Quad-tree
Circuits
Update(sec.) Query (sec.) Per. routing Update(sec.) Query(sec.) Per. routing
S5378 0.02 0.01 0.47% 0.19 <0.01 3.01%
(a)
(b)
Figure 5.1 The routing result of circuit S5378.
Chapter 6 Conclusions
In this thesis, we integrate the algorithm of routing graph reduction into the two-stage routing flow to promote the performance of tile-based router. We also propose a segment tree to help the rip-up and reroute procedure work more flexibly and efficiently. Segment tree maintains the topology of multi-terminal net segment by segment so that the RR procedure just rip-up and reroute the violated segment instead of the entire net. Experiment results show the expeditious routing speed and better routing solution than the multilevel framework. But, the space benchmark limits the improvement of the routing graph reduction.
Bibliography
[1] J. Cong, L. He, C.-K. Koh, and P. Madden, “Performance optimization of VLSI interconnect layout,” Integration VLSI Journal, vol. 21, no. 1–2, pp. 1–94, Nov.
1996.
[2] T. Ohtsuki, “Gridless routers—New wire routing algorithms based on computational geometry, in Proceedings International Conf. Circuits and Systems, pp. 802–809, May 1985.
[3] K. L. Clarkson, S. Kapoor, and P. M. Vaidya, “Rectilinear shortest paths through polygonal obstacles in O(n(log n) ) time,” in Proceedings 3rd Annual Symposium Computational Geometry, 1987, pp. 251–257.
[4] Y. Wu, P. Widmayer, M. Schlag, and C. Wong, “Rectilinear shortest paths and minimum spanning trees in the presence of rectilinear obstacles,” IEEE Transactions on Computers, vol. C-36, no. 1, pp. 321–331, 1987.
[5] S.Zheng, J.S. Lim, and S. Iyengar, “Finding obstacle-avoiding shortest paths using implicit connection graphs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 1, pp. 103-110, Jan. 1996.
[6] J. Cong, J. Fang, and K. Khoo, “An implicit connection graph maze routing algorithm for ECO routing,” in Proceedings International Conference on Computer-Aided Design, pp. 163–167, Nov. 1999.
[7] J. Cong, J. Fang, and K. Khoo, “DUNE: A multilayer gridless routing system with wire plan-ning,” in Proceedings International Symposium Physical Design, Apr.
2000, pp. 12–18.
[8] J. Cong, J. Fang, and K. Khoo, “DUNE - A multilayer gridless routing system,”
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
vol. 20, no. 5, pp. 633–647, May. 2001.
[9] M. Sato, J. Sakanaka, and T. Ohtsuki, “A fast line-search method based on a tile plane,” in IEEE International Symposium Circuits and Systems, pp. 588–591, May 1987.
[10] A. Margarino, A. Romano, A. De Gloria, F. Curatelli, and P. Antognetti, “A tile-expansion router,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-6, pp. 507–517, July 1987.
[11] R. Eric Lunow, “A Channelless, Multilayer Router,” in Proceedings of the 25th ACM/IEEE Design Automation Conference, pp. 667 – 671, 1988.
[12] L. C. Liu, H.-P. Tseng, and C. Sechen, “Chip-level area routing,” in Proceedings International Symposium Physical Design, pp. 197–204, Apr. 1998.
[13] C. Tsai, S. Chen, and W. Feng, “An H-V Alternating Router,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 11, pp.
976–991, Aug. 1992.
[14] J. Dion and L. M. Monier, “Contour: A tile-based gridless router,” Western Research Laboratory, Palo Alto, CA, Research Report 95/3.
[15] Zhaoyun Xing and Russell Kaog, “Shortest Path Search Using Tiles and Piecewise Linear Cost Propagation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 2, pp. 145–158, Feb. 2002.
[16] J. K. Ousterhout, “Corner Stitching: A data-structuring technique for VLSI layout tools,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-3, pp. 87–100, Jan. 1984.
[17] G. Kedem, “The Quad-CIF tree: A data structure for hierarchical on-line algorithms,” in Proc. 19th Design Automation Conf., pp.352-357, June 1982.
[18] H. Samet, “The quadtree and related hierarchical data structures,” Computer Surveys, vol. 16, pp. 187-260, June 1984.
[19] R. L. Brown, “Multiple storage quad trees: A simpler faster alternative to bisector list quad trees,” IEEE Trans. Computer-Aided Design, vol. CAD-5, pp. 413-419, July 1985.
[20] L. Weyten and W. de Pauw, “Quad list quad trees: A geometrical data structure with improved performance for large region queries,” IEEE Trans.
Computer-Aided Design, vol. 8, pp. 229-233, Mar 1989.
[21] J. Cong, M. Xie and Y. Zhang, “An Enhanced Multilevel Routing System,”
in Proceedings IEEE International Conference on Computer Aided Design, San Jose, California, pp 51-58, Nov. 2002.
[22] T.-Y. Ho, Y.-W. Chang, and S.-J. Chen, “Multilevel routing with antenna avoidance,” Proc. ISPD, April 2004.
[23] J.-Y. Li and Y.-L. Li, “An efficient tile-based router with routing graph reduction,” Proc. ISPD, April 2005.