Performance Analysis of the Proposed Dual-Mode Channel Equalizer for

Chapter 4. Simulation Result and Performance Analysis

4.1. Performance Analysis of the Proposed Dual-Mode Channel Equalizer for

To analyze the performance of a proposed scheme, we simulate the PER (%) for different SNR and different CFO, SCO value with CFO and SCO variation being considered. The simulation is processed with multi-paths CM2 channel with data rate 480 (Mb/s). The simulation result is shown in Fig. 4.1. The cross-section view for PER (%) with different CFO, SCO values is shown in Fig. 4.2. From the simulation result, it shows that the proposed PET can track the phase error correctly and compensate the phase error under 60 ppm of CFO, SCO value. Above 60 ppm of CFO, SCO value, resulted ICI and phase error will increase grossly to degrade the system performance. Under IEEE 802.15.3a demanded [2], the CFO, SCO value should be less than total 40 ppm (±20 ppm), and the proposed PET can track the phase error accurately.

Fig. 4.1 PER (%) simulation for different SNR and CFO, SCO value under CM2, data rate 480Mb/s

Fig. 4.2 PER (%) simulation result with different CFO, SCO value in CM2

In most WLAN and WPAN systems, a PER less than 8% is required. Therefore, PER 8% can be the indication of system performance. The PER (%) with different transmission mode and different channel model are shown in Fig. 4.3. and Fig. 4.4.

Simulation results show that for channel model CM4, data rate 110Mbit/s, with the requirement of 8% PER, the proposed design can achieve this demand at SNR 6.98dB. For transmission in AWGN, the proposed scheme can get this demand at

SNR 2.82dB. The comparison of simulation results with system constraint and references is shown in Table 4.1. It shows that the proposed design can achieve 1.36dB to 7.25dB gain in SNR for different simulation conditions.

0 2 4 6 8 10 12

Table 4.1 –Performance Result for UWB system

Entry Proposed [11] [12] System

Constraint AWGN

Data rate=200Mbits/s 3.8 dB 3.8 dB 4.11 dB 5.16 dB AWGN

Data rate=480Mbits/s 6.65 dB 7.2 dB 5.03 dB 9.66 dB CM4 Channel &AWGN

Data rate=200Mbits/s 9.91 dB 14.2 dB 14.18 dB 15.1 dB CM2 Channel &AWGN

Data rate=480Mbits/s 13.85 dB 18.5 dB 15.01 dB 21.1 dB

It should be noted that under the worst environment, CM4, the proposed dual-mode channel equalizer will have 5.19dB gain. In the case of receiving data rate of 480Mbit/s, it will have 7.25dB gain. Hence, the proposed joint scheme makes the receiver more robust to CFO and SCO effects and could suppress the error rate at low SNR with high data rate receiving.

4.2. Performance Analysis of the Proposed Dual-Mode Channel Equalizer for WIMAX system

In WIMAX system, the accuracy of channel estimation is a key factor for system performance. To analyze the accuracy of channel estimation, mean-square-error (MSE) between estimated CFR and real CFR is measured.

Performance of proposed modified-NLMS channel tracker is simulated with condition under SUI-3 channel, 64-QAM modulation. Following is the comparison of MSE between using modified-NLMS channel tracker and without modified-NLMS channel tracker.

Fig. 4.5 MSE analysis of Modified-NLMS channel tracker

The proposed modified-NLMS channel tracker contributes 3~18dB gain in MSE compared with only ZF channel estimation. Fig. 4.6 shows the channel estimation error from sub-carrier number 70 to sub-carrier number 110, between ideal CFR, using modified-NLMS channel tracker and without modified-NLMS channel tracker.

Fig. 4.6 Channel Estimation Error from sub-carrier number 70 to 110

The rate of convergence of modified-NLMS channel tracker depends on the step size. Smaller step size will converge much slower than larger step size. But, smaller step size will contribute smaller MSE than larger step size. Following is the learning curve of proposed modified-NLMS channel tracker with 300 iterations. In this simulation, we select step size with the value equal to 0.0085.

Fig. 4.7 Learning Curve for modified-NLMS channel tracker

Fig. 4.8 shows the bit error rate (BER) with modified-NLMS channel tracker and without modified-NLMS channel tracker under SUI-3 channel, 64-QAM modulation, CFO=0.1 ppm, SCO=16 ppm.

Fig. 4.8 BER Comparison

As it can be seen from Fig. 4.8, design with proposed modified-NLMS channel tracker can contribute 1 dB SNR gain than design without modified-NLMS channel tracker. And, by using modified-NLMS channel tracker, it only result 1 dB SNR loss comparing to use ideal channel. Under different simulation conditions, modified-NLMS channel tracker can contribute different SNR gain. From simulation results, modified-NLMS channel tracker can contribute 1~1.5 dB SNR gain with different simulation conditions.

In 802.16d standard, CFO, SCO value should less than ±8 ppm. With the aid of synchronization, we assume the residual CFO is 0.1 ppm. The BER curves of different transmission mode under SUI-1 to SUI-3 channel, system bandwidth=20MHz, CFO=0.1 ppm, SCO=16 ppm are shown in Fig. 4.9, Fig. 4.10, and Fig. 4.11. Table 4.2 shows the required SNR to attain 10^^-6BER under SUI-3 channel, and also shows the comparison with reference and system constraint.

Fig. 4.9 BER performance under Bandwidth=20 MHz, CFO=0.1 ppm, SCO=16 ppm, SUI-1 channel

Fig. 4.10 BER performance under Bandwidth=20 MHz, CFO=0.1 ppm, SCO=16 ppm, SUI-2 channel

Fig. 4.11 BER performance under Bandwidth=20 MHz, CFO=0.1 ppm, SCO=16 ppm, SUI-3 channel

Table 4.2 –Performance Result for WIMAX system

Entry Proposed [13] System Constraint

BPSK, Code Rate=1/2 10 dB None 11.4 dB

QPSK, Code Rate=1/2 13.7 dB 13.8 dB 14.4 dB QPSK, Code Rate=3/4 15.7 dB 19.6 dB 16.2 dB

16-QAM, Code Rate=1/2 20 dB 18.8 dB 21.4 dB

16-QAM, Code Rate=3/4 22 dB 25.6 dB 23.2 dB

64-QAM, Code Rate=2/3 23.8 dB 29.2 dB 27.7 dB 64-QAM, Code Rate=3/4 27.9 dB 31.5 dB 29.4 dB

From Table 4.2, it can be shown that the proposed dual-mode channel equalizer for WIMAX application can contribute 0.5~3.9dB SNR gain in different simulation conditions.

Chapter 5. Hardware Implementation

5.1. Signal Flow of Dual-Mode Channel Equalizer

The signal flow of proposed dual-mode channel equalizer for UWB system is shown in Fig. 5.1. In the beginning of receiving, it estimates the CFR

H

E (k) by two preambles YL1 (k) and YL2 (k). With the knowledge of these known preambles, the noise power

σ

can be estimated. Then the estimated CFR will be passed through the smoothing filter to reduce the noise effect in channel estimation. After that, the CFR is stored in ram for the following equalization. In the equalization part, it uses the estimated noise power (

σ

E2) and the estimated CFR (HS

(k)) to equalize received

data

Y

(k) under MMSE methodology. After doing equalization, the data phase will

be extracted and sent to PET. In PET part, the phase error will be estimated by pilot sub-carriers. After that, the data sub-carriers are compensated according to these estimated phase errors. Finally, the compensated data sub-carriers are sent to De-Mapper.

For WIMAX system, signal flow is shown in Fig. 5.2. Except for the raised-cosine interpolator, modified-NLMS channel tracker, the signal flow compared to UWB is almost the same. Consequently, most functional blocks, such as divider, smoothing filter, PET, tan^-1 ...etc, can be reused to save hardware resource.

2-parallelism architecture is used to meet high sample rate up to 528 MHz for UWB. The architecture of each functional block is introduced as following sections.

Fig. 5.1 Signal Flow of Proposed Channel Equalizer for UWB

Fig. 5.2 Signal Flow of Proposed Channel Equalizer for WIMAX

5.2. Architecture of Dual-Mode Channel Estimator

Fig 5.3 shows the architecture of dual-mode channel estimator. In UWB mode, dual-mode channel estimator will turn on two parallel data paths. According to pre-defined UWB preamble, look-up table (LUT) combined with following adder and multiplier performs the ZF channel estimation. In this mode, control circuit selects C1 constant ( 2 ) as an input to the multiplier. Once ZF channel estimation has been done, the estimated CFR will be stored in UWB ram. In WIMAX mode, maximum sample rate is only 32MHz. In order to save power consumption, only parallel 1st data path is turned on. In this mode, control circuit selects C2 constant (1/ 2 ) as an input to the multiplier. After doing ZF channel estimation, the signal will be sent into 6-taps raised-cosine interpolator to interpolate the CFR of odd data sub-carriers. After doing interpolation, CFR of all data sub-carriers are stored in WIMAX ram.

Fig. 5.3 Architecture of proposed dual-mode channel estimator

For UWB mode, MMSE equalizer is used to equalize the distorted signal. To use MMSE methodology, information of noise power is needed. So, two received preambles of UWB are used to estimate the noise power in proposed dual-mode channel estimator. Fig. 5.4 shows the architecture of noise power estimator. When first received preamble is coming, it will be stored in UWB ram. When second received preamble is coming, first preamble will be read out. And, these two preambles are sent to subtractor. These subtracted values are then sent to the square circuit, calculating the noise power of each sub-carrier. Finally, the mean average of noise power which can be used for following MMSE equalization is calculated.

| |2

Fig. 5.4 Architecture of noise power estimator

For WIMAX system, only even sub-carriers are utilized in long preamble.

Interpolator is needed to get the CFR of odd sub-carriers. Fig. 5.5 shows the architecture of 6-tap raised-cosine interpolator. Where C1, C2, C3 are constant terms calculated by raised-cosine function. Fig. 5.6 shows the operation of the 6-tap raised-cosine interpolator. At the beginning, the CFR of DC sub-carrier is interpolated at first. Then, CFR of DC sub-carrier can be used to interpolate other CFR of odd sub-carriers.

Fig. 5.5 Architecture of 6-tap raised-cosine interpolator

10, 6, 2, 2, 6, 10

H_- H_- H_- H H H

100, 98, 98, 100

H_- H_- KH H

Fig. 5.6 Operation of 6-tap raised-cosine interpolator

5.3. Architecture of Dual-Mode Equalizer

For frequency domain one-tap equalizer, operation of MMSE equalization and ZF equalization is just complex division. Difference of MMSE equalization and ZF equalization is the usage of estimated noise power. For MMSE equalization, estimated noise power is added in denominator and then sent to the real divider. For ZF equalization, denominator is added with zero value.

For UWB mode, MMSE equalizer is used to equalize distorted signals. Under consideration of high sampling rate for UWB application, two parallel data paths are turned on to do MMSE equalization. For WIMAX mode, to save power consumption, only parallel 1st data path is turned on. The architecture of proposed dual-mode equalizer is shown in Fig. 5.7. The design of real divider is introduced below.

Fig. 5.7 Architecture of dual-mode equalizer

For real divider design [14], the multi-cycle division is used. The concept is to separate one cycle into many cycles and get quotient by iterative subtraction. At first, we define the format of the signed number, where m is the total bits and n is the bits of decimal. Assuming the format of input signal is (m1,n1), and the format of output signal is (m2,n2). At first, in order to normalize the quotient to saturation point, dividend is shifting (m2-n2-1) bits right. And, in first stage of single iterative unit, A is the dividend >> (m2-n2-1), and B is the divisor. If A is larger than B, the q(k) will be “1” else not, it can be determined by the sign bit of subtraction result. q(k) is just the inverse of the sign bit of sub. Then, we update A by (sub<<1) or (A<<1) depends on the sign bit of sub. Updated A, B and q(k) are then buffered in pipelined register, and will be sent to the next iterative unit to get the next bit of quotient. The relationship is shown in Table 5.1. The architecture of pipelined real divider is shown in Fig. 5.8.

Table 5.1 – Relationship of operation in single iterative unit

Sub>=0 Sub<0

Sign bit 0 1

q(k) 1 0

Updated “A” Sub<<1 A<<1

Fig. 5.8 Architecture of pipelined real divider

5.4. Architecture of Dual-Mode Phase Error Tracker and Compensator

Fig. 5.9 shows the architecture of proposed dual-mode phase error tracker and compensator. In this design, Cordic (Coordinate Rotation Digital Computer) is used to extract the phase information of the signal. And, De-Cordic has two different utilities. One is used to covert the signal in Magnitude-Phase domain to Real-Imaginary domain, and the other is used to rotate the signal according to the given phase. The algorithm of Cordic, De-Cordic will be introduced later. As it can be seen from the Fig. 5.9, the phase of pilot sub-carrier extracted by Cordic is pre-compensating with the previous tracker phase error (_l_₁  K _l_₁). And, this pre-compensated value is use to calculate the mean phase error and phase error slope.

Then, mean phase error and phase error slope are combined by phase error combiner to form the total tracked phase error. Then, tracked phase error can be used to compensate the received data by data compensator. Finally, compensated data is passing through De-Cordic to return Magnitude-Phase domain to Real-Imaginary domain. Also, in UWB mode, two data paths are turned on. In WIMAX mode, only upper data path, shown in Fig. 5.9, is turned on to save the power consumption.

Fig. 5.9 Architecture of dual-mode phase error tracker and compensator

Cordic [15] is an iterative algorithm used to acquire amplitude and angle from a 2x1 signal vector (Rectangular-to-polar mode). General methods to realize these functions need LUTs, complex-valued multipliers, and dividers. Cordic reduces complexity by using simple components, like adders, comparators and shifters. The accuracy of the Cordic increases with larger iterative number. After the last iteration has been done, the signal is multiplied by the factor A. Following is the

i-th iterative formula of Cordic algorithm:

58 shows the architecture of pipelined Cordic.

De-Cordic is designed to rotate a 2x1 vector with a certain angle (phase-rotation mode). The algorithm for De-Cordic is the same with the Cordic. So, the architecture of De-Cordic is also the same with Cordic.

-Fig. 5.10 Architecture of pipeline cordic

5.5. Architecture of Modified-NLMS Channel Tracker

In WIMAX system, only even sub-carriers are utilized in long preamble. If the interpolator is not ideal, the aliasing effect will result in channel estimation error.

Otherwise, time variant characteristic will also result in channel estimation error.

And, channel estimation error will degrade the performance of equalization. So, in WIMAX mode, modified-NLMS channel tracker is turned on to mitigate the channel estimation error. The architecture of modified-NLMS channel tracker is shown in Fig. 5.11. Gradient term calculation part is just a complex divider, which is also used in dual-mode equalizer. And, there are two complex dividers in design of dual-mode equalizer. In WIMAX mode, only one complex divider is turned on and the other is turned off. So we can reuse this idle complex divider to do gradient term calculation and save hardware resource. Based on the same consideration, De-Cordic which is used in phase error tracker and compensator can also be reused.

Delay Lines are used to hold on signals. In WIMAX mode, UWB ram is in idle state.

So, UWB ram is used to hold on signals which are inputs to modified-NLMS channel tracker.

D %

D % m

Fig. 5.11 Architecture of modified-NLMS channel tracker

5.6. Architecture of Dual-Mode Channel Equalizer

Following shows the total architecture of proposed dual-mode channel equalizer. In UWB mode, two data paths will be turned on. All signals will pass through the upper paths of multiplexers. In WIMAX mode, all signals will pass through the lower paths of multiplexers.

Fig. 5.12 Architecture of Dual-Mode Channel Equalizer

5.7. Implementation Issues

Hardware cost and system performance are trade-off in hardware implementation, so fixed-point simulation will be needed, before the implementation.

Following figure shows the simulation result. According to the Fig 5.13, when the resolution is lower than 12 bits, the system performance will degrade seriously. So, 12-bit resolution is chosen to do the hardware implementation.

Fig. 5.13 Fixed Point Simulation

5.8. Hardware Implementation Results

In this section, we discuss the implementation of the proposed dual-mode channel equalizer. We use SYNOPSYS design compiler to synthesis the RTL file with UMC 0.18 slow library. All functional blocks are synthesized with clock rate equal to 270 MHz. Gate count of each functional block is shown in Table 5.2.

Without considering the dual-mode design, gate count of single-mode channel equalizer for WIMAX and UWB is shown in Table 5.3. As it can be seen from Table

5.2 and Table 5.3, dual-mode channel equalizer utilizes most of common functional blocks can elevate the hardware efficiency and save hardware resource. Gate count of dual-mode channel equalizer which can deal with two different signals for UWB and WIMAX systems is only 130k.

Table 5.2 – Synthesis Report for Each Module

Module Gate Count

Table 5.3 – Synthesis Report for Single-Mode Channel Equalizer

Module Gate Count consumption of dual-mode channel equalizer is 47.38mW. For UWB application, clock rate is 270 MHz, and corresponding power consumption is 72.56 mW.

5.9. FPGA Prototyping

In FPGA prototyping, the input bit pattern is generated from MATLAB. Then, input the generated bit pattern through emulation tool of VeriComm Pro of SMIMS TECHNOLOGY CORPORATION to FPGA. Then, the resulted waveform will be sent back to the tool of VeriComm Pro to dump the file for checking. For FPGA verification, register file will be used to take place RAM. In UWB system, three bands CFR need be stored and bit resolution of the proposed dual-mode channel equalizer is twelve. So, total bits need to be stored in register file are 3*2*12*128=9216 bits. In proposed dual-mode channel equalizer, we use twelve 12*64 bits of register file to store three bands CFR. For WIMAX application, total bits need to be stored in register file are 2*12*256=6144 bits. So, we use two 12*256 bits of register file to store the WIMAX CFR. The FPGA verification plan is shown in Fig. 5.14. Fig. 5.15 shows the verifying situation. Fig. 5.16 shows the synthesis report for 12*64 bits of register file. Fig. 5.17 shows the synthesis report for 12*256 bits of register file. Fig. 5.18 shows the FPGA synthesis report for proposed dual-mode channel equalizer.

Fig. 5.14 FPGA verification plan

Fig. 5.15 FPGA Board

Fig. 5.16 Synthesis Report for 12x64 bits of Register file

Fig. 5.17 Synthesis Report for 12x256 bits of Register file

Fig. 5.18 Synthesis Report of Dual-Mode Channel Equalizer

5.10. FPGA Emulation

Fig. 5.19 shows the FPGA emulation result and Fig. 5.20 shows the RTL simulation result. According to these two figures, FPGA emulation result is the same with RTL simulation result.

Fig. 5.19 FPGA Emulation

Fig. 5.20 RTl Simulation

FPGA emulation result is sent back to Matlab and plot the constellation diagram. Fig. 5.21 shows the FPGA emulation result under 64-QAM, SUI-2 channel, CFO=0.1 ppm, SCO=16 ppm , SNR=30 dB. Fig. 5.22 shows the floating point simulation result with Matlab under the same conditions. As we can see from these two figures, hardware design of proposed dual-mode channel equalizer can equalize the distorted signal correctly.

Fig. 5.21 FPGA Emulation Result Fig. 5.22 Matlab Simulation Result

Chapter 6. Conclusions and Future Work

6.1. Conclusions

In this thesis, we proposed a dual-mode channel equalizer which can be applied to UWB and WIMAX systems. It is robust to solve multi-path channels, CFO, SCO effect, as well as AWGN. Simulation results show that the proposed dual-mode channel equalizer works even better in harsh channel conditions. In UWB system simulation, the proposed dual-mode channel equalizer can contribute 1.36 ~ 7.25dB gain in SNR for different simulation conditions. Also, for WIMAX system simulation, the proposed dual-mode channel equalizer can also contribute 0.5 ~3.9 dB SNR gain. Moreover, the proposed low complexity PET which uses only pilot sub-carriers to track the phase error is very compatible for all OFDM based system.

For hardware implementation, most functional blocks are reused to save hardware resource. 2-parallelism architecture is used to meet high sampling rate up to 528

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