Table 5-1 Comparison of poly-Si TFTs formed by a furnace-crystallization with
various gate dielectrics of LaAlO3, Al2O3, LPCVD SiO2, and PECVD
TEOS oxides.
ix
Figure Captions
Chapter 1 Introduction
Fig. 1-1 The evolution of CMOS technology requirements (ITRS 2005).
Fig. 1-2 The band offset of popular high-κ materials.
Fig. 1-3 The values of work function for different metal materials.
Chapter 2 High temperature stable IrxSi Gates with High Work Function on HfSiON p-MOSFETs
Fig. 2-1 C-V characteristics of HfSiON/n-Si with IrxSi, Ir and Al gates capacitors.
The device areas are 100 μm × 100 μm.
Fig. 2-2 J-V characteristics of HfSiON/n-Si with IrxSi, Ir and Al gates capacitors.
Fig. 2-3 XRD profiles of Ir3Si/HfSiON structures.
Fig. 2-4 SIMS profile of Ir3Si gates on HfSiON at different RTA temperature. The
Ir3Si accumulated toward HfSiON interface is found to un-pin the
Fermi-level.
Fig. 2-5 The Id-Vd characteristics of Ir3Si/HfSiON p-MOSFETs.
Fig. 2-6 The Id-Vg characteristics of Ir3Si/HfSiON p-MOSFETs.
Fig. 2-7 The extracted hole mobilities from Id-Vg characteristics of Ir3Si/HfSiON
p-MOSFETs.
Chapter 3 HfSiON n-MOSFETs Using Low Work Function HfSix Gates
Fig. 3-1 C-V characteristics for high temperature RTA formed HfSix/HfSiON and low temperature Al/HfSiON capacitors. The device area was 100 μm×100
μm.
Fig. 3-2 J-V characteristics for high temperature RTA formed HfSix/HfSiON and
low temperature Al/HfSiON capacitors.
Fig. 3-3 The Id-Vd characteristics of HfSix/HfSiON n-MOSFETs. The
amorphous-Si on HfSiON was 5 nm and gate length was 10 μm.
Fig. 3-4 The Id-Vg characteristics HfSix/HfSiON n-MOSFETs. The amorphous-Si
on HfSiON was 5 nm and gate length was 10 μm.
Fig. 3-5 The electron mobilities of HfSix/HfSiON n-MOSFETs.
Chapter 4 Novel High-κ HfLaON n-MOSFETs with Preserved Amorphous State to 1000oC
Fig. 4-1 Grazing incident XRD spectra of HfLaO after different RTA temperature.
Fig. 4-2 Grazing incident XRD spectra of HfLaON with NH3 plasma after different
RTA temperature. In contrast to the HfLaO case, HfLaON stays
amorphous state after 1000oC RTA.
xi
Fig. 4-3 XPS spectra of HfLaON after 1000oC RTA. The existence of Hf, La, O,
and N is clearly seen.
Fig. 4-4 TEM image of TaN/HfLaON/Si after 1000oC RTA. Good interface
property is observed with very thin interfacial layer.
Fig. 4-5 J-V characteristics of 1000oC-annealed TaN/HfLaON n-MOS capacitors
with various N+ nitridation.
Fig. 4-6 C-V characteristics of 1000oC-annealed TaN/HfLaON n-MOS capacitors
with various N+ nitridation.
Fig. 4-7 C-V characteristics of TaN/HfLaON n-MOS capacitors after different
temperature RTA. The device area was 100 μm×100 μm.
Fig. 4-8 J-V characteristics of TaN/HfLaON n-MOS capacitors after different
temperature RTA.
Fig. 4-9 SIMS profile of TaN gate on HfLaON at different temperature RTA. No Ta
penetration through HfLaON can be found.
Fig. 4-10 The comparison of gate leakage current density for MOS devices with
SiO2 and HfLaON gate dielectrics.
Fig. 4-11 The dielectric constant of HfLaON at different RTA temperature.
Significant higher κ value at high RTA temperature is obtained than HfO2.
Fig. 4-12 The Id-Vd characteristics of TaN/HfLaON n-MOSFETs fabricated at
1000oC RTA thermal cycle.
Fig. 4-13 The Id-Vg characteristics of TaN/HfLaON n-MOSFETs fabricated at
1000oC RTA thermal cycle.
Fig. 4-14 The electron mobilities of TaN/HfLaON n-MOSFETs fabricated at 1000oC
RTA thermal cycle.
Fig. 4-15 The ΔVt of TaN/HfLaON n-MOSFETs stressed at 85oC and 10 MV/cm
for 1 hour.
Chapter 5 Poly-Silicon Thin Film Transistors Using Ytterbium Metal Gate and LaAlO3 Dielectric
Fig. 5-1 C-V hysteresis of 50 nm LaAlO3 gate dielectric with 400oC 30 min furnace
O2 treatment after sweeping between 5V and -5V. The ΔVhys is smaller
than 70 mV.
Fig. 5-2 The gate current density vs. electric field relation for LaAlO3 gate dielectric
poly-Si TFT.
Fig. 5-3 The Id-Vg characteristics of the Yb/LaAlO3 poly-Si TFT measured at Vds =
0.1 V.
Fig. 5-4 The Id-Vd characteristics of the Yb/LaAlO3 poly-Si TFT.
Fig. 5-5 The gate voltage shift of Yb/LaAlO3 poly-Si TFT under constant-current
1
Chapter 1 Introduction
1.1 Overview of high-κ gate dielectrics
The gate leakage current through the gate oxide increases significantly because direct tunneling is the primary conduction mechanism in down-scaling CMOS
technologies. To reduce the leakage current related higher power consumption in
highly integrated circuit and overcome the physical thickness limitation of silicon
dioxide, the conventional SiO2 will be replaced with high dielectric constant (high-κ)
materials as the gate dielectrics beyond the 65 nm technology mode [1]-[6]. Therefore,
the engineering of high-κ gate dielectrics have attracted great attention and played an
important role in VLSI technology. Although high-κ materials often exhibit smaller
bandgap and higher defect density than conventional silicon dioxide, using the high-κ
gate dielectric can increase efficiently the physical thickness in the same effective
oxide thickness (EOT) that shows lower leakage characteristics than silicon dioxide
by several orders without the reduction of capacitance density [2]-[5]. According to
the ITRS (International Technology Roadmap for Semiconductor) [7], the suitable
gate dielectrics must have κ value more than 8 for 50-70 nm technology nodes and
that must be more than 15 when the technology dimension less than 50 nm. Fig. 1-1
shows the evolution of CMOS technology requirements.
Research on finding an appropriate substitute to the superior SiO2 has been going
on for almost a decade. Oxy-nitrides (SiOxNy) have been introduced to extend the use
of SiO2 in production but eventually it has to be replaced by a high-κ material, such as
Ta2O5,TiO2, HfO2, ZrO2, Al2O3, La2O3 or mixtures of them or metal-oxide-silicates of
the mentioned compounds. However, most metal oxides will have the characteristics
of crystallization at elevated temperature which cause devices generate non-uniform
leakage distribution and give large statistical variation for nano-meter devices across
the chip. Therefore, replacement gate strategies have been proposed to prevent
crystallization and deleterious effects of mass and electrical transport along grain
boundaries. Fig. 1-2 shows the summaries of the κ value and band offset for popular
high-κ dielectric candidates.
1.2 Overview of metal gate electrodes
The gate electrode in CMOS devices is conventionally made of highly doped
polycrystalline silicon (poly-Si). However, as the CMOS technology down-scaling,
poly-Si gate will encounter several inherent limitations. One of them is depletion of
the poly-Si electrode when the gate stack is biased in inversion [8]-[20]. The depleted
region is added to the dielectric thickness, which results the increase of EOT and
degradation of the transconductance. Increased resistance of the gate electrode fingers
3
is another issue due to the scaling geometry. Besides, diffusion of boron penetrates
from the poly-Si gate will also degrade the performance of the transistors.
To overcome these problems, using metal gate electrodes will be a practical way
to eliminate poly gate depletion and boron penetration [8]-[15]. In addition, metal
gates also show the potential of reduced sheet resistance. However,
metal-gate/high-κ CMOSFETs show undesired high threshold voltages (Vt), which is
opposite to the VLSI scaling trend. This phenomenon is known as “Fermi-level
pinning”, although the background physics may be attributed to interface dipole
and/or charged defects [8]. Moreover, thermal stability of the effective metal electrode
and metal diffusion are also important considerations.
The work functions (Φm) of metal shown in Fig. 1-3 play an important role for
metal-gate/high-κ CMOSFETs. The preferred work function of the metals are ~5.2 eV
for p-MOSFETs and ~4.1 eV for n-MOSFETs. Recently, lots of metal or metal-nitride
materials have been widely researched and successfully intergraded in advanced
CMOSFETs, such as TiN, TaN, Pt, Mo and Ir [8]-[20]. However, it has been found
that thermal annealing of the metal gates at temperatures above 900oC results in
mid-gap values for almost all metal gate candidates. Therefore, the Fermi-level
pinning effect needs to be avoided by selecting suitable metal gate and high-κ
materials for advanced CMOS technologies.
1.3 Innovation and Contribution
To compensate Fermi-level pinning effect, low and high work function metal
electrodes are required to reduce the pinning effect for n- and p-MOSFETs,
respectively. For p-MOSFETs, high work function metal electrodes larger than the 5.2
eV of p+ poly-Si are needed. However, only Ir (5.27 eV) and Pt (5.65 eV) in the
Periodic Table [21] can meet this requirement, which make the
metal-gate/high-κ p-MOSFETs especially challenging [8]-[10]. Ir is more preferable
than Pt due to a simpler etching process by reactive ion etching (RIE) [22]-[23].
Unfortunately, large metal diffusion through high-κ dielectrics was found in pure Ir
gates after 1000oC RTA which caused p-MOS device failures [24]-[25]. Another
possibility is using low temperature full silicidation (FUSI) gates [9],[24]-[27].
However, the p-MOS devices incorporating high work function PtxSi or IrxSi still
failed to integrate into the CMOS SALICIDE process due to the lack of required
selective wet etching of Pt or Ir during SALICIDE. In this thesis, we have proposed
and demonstrated a new high temperature stable IrxSi FUSI gate on high-κ HfSiON
with a proper effective work function of 4.95 eV. HfSiON has good metal diffusion
barrier property and the good compatibility with currently used SiON gate dielectric
with added Hf for higher κ value.
For n-MOS application, we have used the similar method of IrxSi for p-MOS to
5
develop the low work function HfSix gate for n-MOSFETs. This is because the Hf has
very low work function of 3.5 eV in the Periodic Table. The HfSix gate on HfSiON,
formed by Hf deposition on thin amorphous Si, gives a low effective work function of
4.27 eV. In addition, the HfSix/HfSiON can sustain a high rapid thermal annealing
(RTA) temperature of 1000◦C that is compatible with current VLSI process line.
Since both process and mechanism of HfSix and IrxSi, with respective low and high
effective work function, are the same, these results indicate the high possibility to
realize dual work function metal-gate/high-κ CMOS with large work function
difference.
Besides, we also developed the novel HfLaON gate dielectric with simple TaN
metal gate, good device integrity with a low effective work function of 4.24 eV has
been obtained for n-MOSFETs. The preserved 1000oC amorphous state is similar to
currently used SiO2 or SiON, with additional merit of full process compatibility with
VLSI fabrication lines.
Finally, we have integrated low work function ytterbium (Yb) metal gate with
high-κ LaAlO3 dielectric into low-temperature poly-Si (LTPS) thin film transistors
(TFTs). Good TFT performance was achieved - such as a high drive current, low
threshold voltage and sub-threshold slope, as well as an excellent on/off current ratio
and high gate-dielectric breakdown field. This was achieved without hydrogen
passivation or special crystallization steps. The good performance is related to the
high gate capacitance density and small equivalent-oxide thickness provided by the
high-κ dielectric.
1.4 Thesis Organization
This dissertation focused on the characterization of alternative metal gates and
high-κ dielectric materials for the sub-45 nm technology node. In this chapter, the
history of high-κ dielectrics and metal gate electrode evolution and the key materials
have been reviewed. Chapter 2, 3, and 4 deeply study the IrSix gate on HfSiON for
p-MOS, HfxSi gate on HfSiON for n-MOS, TaN gate on HfLaON for n-MOS,
respectively. Chapter 5 presents the study of Yb metal gate combining with a high-κ
LaAlO3 dielectric into low-temperature poly-Si TFTs. A summary and suggestion are
presented in chapter 6.
7
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11
Fig. 1-1 The evolution of CMOS technology requirements (ITRS 2005).
Fig. 1-2 The band offset of popular high-κ materials.
13
Fig. 1-3 The values of work function for different metal materials.
Chapter 2
High temperature stable Ir
xSi Gates with High Work Function on HfSiON p-MOSFETs
2.1 Introduction
To continue down-scaling VLSI technology and increase the integration density,
high-κ gate dielectrics are needed for MOSFETs to reduce the large dc power
consumption from gate leakage current [1]-[10]. In addition, metal gates are required
to eliminate poly gate depletion. However, metal-gate/high-κ CMOSFETs show
undesired high threshold voltages (Vt), which is opposite to the VLSI scaling trend.
This phenomenon is known as “Fermi-level pinning” [1], although the background
physics may be attributed to interface dipole and/or charged defects [1], [8]. To
compensate this Fermi-level pinning effect, high work function metal electrodes
larger than the 5.2 eV of p+ poly-Si are needed. However, only Ir (5.27 eV) and Pt
(5.65 eV) in the Periodic Table [11] can meet this requirement, which make the
metal-gate/high-κ p-MOSFETs especially challenging [1]-[2]. Ir is more preferable
than Pt due to a simpler etching process by reactive ion etching (RIE) [12]-[13].
Unfortunately, large metal diffusion through high-κ dielectrics was found in pure Ir
gates after 1000oC RTA which caused p-MOS device failures [7]-[8]. Previous
15
attempts by using IrN to improve the thermal stability also failed due to weak Ir-N
bonding strengths, where IrN decomposition and penetrating high-κ dielectrics were
found after high temperature RTA [8]. Another possibility is using low temperature
full silicidation (FUSI) gates [3]-[9]. However, the p-MOS devices incorporating high
work function PtxSi or IrxSi still failed to integrate into the CMOS SALICIDE process
due to the lack of required selective wet etching of Pt or Ir during SALICIDE.
To overcome this problem, we have proposed and demonstrated a new high
temperature stable IrxSi FUSI gate on high-κ HfSiON. This is different from the low
temperature FUSI process [3]-[6] since it is formed first before ion implantation and
undergoes 1000oC RTA thermal cycle for implant activation. To achieve this high
temperature stability goal, additional Si was inserted between Ir and high-κ HfSiON,
where less Fermi-level pinning was obtained by forming Ir-rich IrxSi gates. High-κ
HfSiON also has good metal diffusion barrier property [14]-[15], which is similar to
our previous HfAlON [7]-[8] but it has the important advantage of better
compatibility with currently used SiON gate dielectric with added Hf for higher
κ value. After 1000oC RTA, IrxSi/HfSiON p-MOSFETs show good device integrity
of a high effective work function (φm-eff) of 4.95 eV, a small Vt of -0.15 V and a peak
hole mobility of 84 cm2/V-s. These results are compatible with and even better than
the best reported metal-gate/high-κ p-MOSFETs [5]-[9].
2.2 Experimental procedure
The gate-first IrxSi/HfSiON p-MOSFETs were fabricated on 12-in N-type Si
wafers with resistivity of 1~10 Ω-cm. After RCA cleaning, 4 nm HfSiO dielectric
(Hf/(Hf+Si) = 50%) was deposited by atomic-layer deposition (ALD). HfSiON gate
dielectric was formed by applying NH3 plasma surface nitridation on HfSiO [16].
After post-deposition annealing (PDA), 5~30 nm amorphous Si and 20~30 nm Ir were
deposited by PVD [7]. For Ir/Si/HfSiON capacitors, a 1000oC RTA was applied for 10
sec to form IrxSi gates. For MOSFETs, additional 400 nm Si was deposited on top of
Ir/Si to avoid ion implantation penetrating through the thin Ir/Si. After gate definition,
Boron was implanted at 25 KeV energy and 5×1015 cm-2 dose, and activated at
1000oC RTA for 10 sec. Meanwhile, IrxSi was also formed during RTA, where the x=3
was determined by x-ray diffraction measurements. Note that this process is different
was determined by x-ray diffraction measurements. Note that this process is different