Chapter 3 Concurrent Dual-Band LNA
3.2 Principle of the Circuit Design
In this section, the design principle of the concurrent dual-band LNA is introduced. Fig.3.1 is the schematic of the circuit of the concurrent dual-band LNA with 3 step gain. The principle emphasizes on the concurrent dual-band input and output impedance matching, noise analysis and variable gain function.
Fig.3.1 Schematic of the Concurrent Dual-Band LNA with 3 Step Gain
3.2.1 Dual-Band Input Matching
Fig.3.2 (a) The Input Stage of the Concurrent Dual-Band LNA (b) Equivalent Model
The input stage of the LNA is shown in Fig.3.2 (a). The method of input matching network is similar to that of the source inductance degeneration. The input impedance can be derived from Fig.3.2 (b). If the capacitance C is neglected, the gd input impedance can be expressed as in the following
1 )
where the real part of the input impedance can be re-expressed as
And the image part of the input impedance can be re-expressed as
)
where the image part of the input impedance will be zero at the two desired resonance frequencies.
Therefore, the dual-band input matching can be achieved by the method of the L-degeneration with a LC-tank in series [5].
3.2.2 Dual-Band Gain Analysis
To analyze the overall input stage’s trans-conductance Gm of the concurrent dual-band LNA, we neglect the contribution of subsequent stages and the overlap capacitance Cgd. After some small signal calculation, the overall trans-conductance of the concurrent dual-band LNA at operating two frequencies can be expressed as
)
where Qin is the effective Q of the amplifier input circuit.
The overall trans-conductance is independent of the device trans-conductance.
This result is the consequence of two competing effects that that cancel precisely. If narrowing device without changing any bias voltage, the device trans-conductance would decrease by the same factor as the width. However, the gate capacitance would also shrink by the same factor, and the inductances would have to increase to maintain
resonance. Since the ratio of inductance to capacitance increase, the Q of input network must increase. The increase in Q cancels precisely the reduction in device trans-conductance, so that the overall trans-conductance remains unchanged.
3.2.3 Noise Analysis
The input stage of the concurrent dual-band LNA is similar as the cascode LNA with L-degeneration. Therefore, the method of noise analysis is also similar. In a similar way, the analysis neglects the contribution of subsequent stages to the amplifier noise figure.
2
igc i2gu
2
vrg
2d
i
2
vLg 2
1
vL
Fig.3.3 Equivalent Noise Model of the Concurrent Dual-Band LNA Input Stage
The equivalent noise model of the input stage is shown in Fig.3.3. The noise current i represents the channel thermal noise of the device, and d2 igc2 , i2gu are the
gate noise current with correlated and uncorrelated term. The noise voltage vrg2 is
the thermal noise of the gate resistor of NMOS, and vLg2 and v represent the L21 thermal noises of the parasitic resistor of the on-chip inductor.
The noise figure of concurrent dual-band LNA at resonant frequencies can be expressed as
)
3.2.4 Dual-Band Output Matching
Fig.3.4 Output Matching Network of the Concurrent Dual-Band LNA
Fig.3.4 is the output matching network of the concurrent dual-band LNA. The output loading Zload is composed of L2, L3, C2 and C3, which can be represented as
1 )
The output load Zload makes the impedance’s real part of the desired two bands
to the 50 . Then the output capacitance C4 pulls the image part of the output impedance to the zero.
3.2.5 Step Gain Function
The noise figure is dictated by the sensitivity specification of the receiver to provide the weakest received signal. LNA should provide enough gain to suppress the noise of the following stage. But under strong received signal conditions, LNA and the whole receiver gets saturated and degrades the linearity performance. Hence, the large amplitude range of signals requires variable gain to enhance the linearity of overall system. Variable gain function enhances the signal-to-noise ratio, in presence of minimum amplitude signals, while not saturating the last stages of the receiver, in presence of maximum amplitude signals.
One of the popular methods of controlling the gain of the cascode LNA is by diverting a portion of drain current from the cascade transistor through another MOSFET. This method of gain control significantly degrades the NF and affects the input matching network. Another method controls the gate bias of the PMOS transistor in the folded cascade topology and does not sacrifice the noise figure in low gain mode. But in high gain mode, the power consumption may be large due to the low trans-conductance of the PMOS transistor.
The adoptive method of control gain in the circuit is resistor-chain gain control technique [7]. This method can maintain the same power consumption and hold the input matching with less noise figure degradation in different gain modes. The circuit is shown in Fig.3.5.
Resistors R1, R2 and R3 in series form a resistor chain. In the high gain mode, MOS transistor M2 turns on while M3 and M4 are disabled. Hence, M2 functions as
the cascode transistor. The gain of the LNA is the highest in this mode because the output current from the forward stage is injected to output without voltage dividing.
The medium gain mode is realized by disabling M2 and M4, and letting M3 be the cascode transistor. Thus the output current from the forward stage is injected through M3. In low gain mode, the output current from the forward stage is injected through M4, which has the lowest resistance in the resistor chain. In this gain control scheme, gain steps depend on the ratios and values of the resistance chain.
Fig.3.5 Resistor-Chain Gain Control Technique
LNA input impedance is almost independent of the gain modes because it depends only on the input matching network. Since both signal and noise currents of
the forward stage is injected into the same node in the resistor chain, the output SNR and the noise figure of the LNA are degraded only slightly in low gain modes. The disadvantage of this technique is that the gain step is sensitive to parasitic impedance in the resistor chain and the impedance transformation network.