Chapter 2 PLL overview
We give the overview of phase-locked loop (PLL), including LPLL, DPLL and ADPLL.
Chapter 3 Proposed Low Power Digitally Controlled Oscillator (DCO)
We introduce many kinds of digitally controlled oscillator and propose the low power digitally control oscillator.
Chapter 4 Proposed Low Power ALL Digitally Phase-Locked Loop (ADPLL) We introduce the algorithm and architecture of conventional ADPLL which is proposed by Motorola in 1995. And, We present a low power search algorithm and multi-time phase frequency detector and state the circuit design in each function block such as control unit, enable generator match delay line..
Chapter 5 Application and simulation result
Chapter 2 PLL overview
In this chapter, we will review three kinds of phase locked-loop circuit [2.1], they are: Linear PLL (LPLL), Digital PLL (DPLL), and All-Digital PLL (ADPLL).
The very first phase locked-loops (PLLs) were implemented as early as 1932 by de Bellescize; this French engineer considered the inventor of coherent communication.
The PLL found broader industrial applications only when it becomes available as an integrated circuit.
The first PLL ICs appeared around 1965 and were purely analog devices. In the following years the PLL drifted slowly but steadily into digital territory. The very first digital PLL (DPLL), which appeared around 1970, was in effect a hybrid device. A few years later, the all-digital PLL (ADPLL) was invented. The ADPLL is exclusively built from digital function blocks and hence do not contain any passive components like resistor and capacitors. Different types of PLLs behave differently.
Classifications of PLL circuit
(1) LPLL: Linear PLL. Each block is analog.
(2) DPLL: Digital PLL. Phase Detector is digital and the others are analog.
(3) ADPLL: All Digital PLL. Each block is digital. Loop filter is from Up/Down counter. VCO (Voltage Controlled Oscillator) is from DCO (Digital Controlled Oscillator).
2-1 The operating principle of PLL
A PLL is a circuit which causes a particular system to track with another one.
More precisely, a PLL is a circuit synchronizing an output signal (generate by an oscillator) with a reference or input signal in frequency as well as in phase. In the synchronized—often called locked—state the phase error between the oscillator’s output signal and the reference signal is zero, or very small. If phase builds up, a control mechanism acts on the oscillator in such a way then the phase error is again reduced to a minimum. In such a control system the phase of the output signal is actually locked to the phase of the reference signal. This is why it is referred to as a phase-locked loop. The operating principle of the PLL is explained by the example of the linear PLL. [2.2]
Figure 2-1 Block diagram of the PLL
In the Figure 2-1, the signals of interest within the PLL circuit are defined as follows:
U1(t): the reference(or input ) signal
ω1: the angular frequency of the reference signal U2(t): the output signal of the VCO
ω2 : the angular frequency of the output signal Ud(t): the output signal of the detector
Uf(t): the output signal of the loop filter
Θe: the phase error define as the phase difference between signals U1(t) and U2(t)
Now we look at the operations of the three functional blocks in the Figure 2-1.
Functional Blocks：
VCO:
VCO generate an angular frequency ω2 ,which is determined by the output signal Uf of the loop filter. The angular frequency ω2 is given by equation (2.1) , where ω0 is the center frequency of the VCO and the K0 is the VCO gain.
Equation2.1 is plotted graphically in the Figure 2-2.
ω2 =ω0 + K0 x Uf(t) (2.1)
Phase Detector:
the Phase Detector compares the phase of the output signal of VCO with the phase of reference signal and generate an output signal Ud(t) which is approximately
proportional to the phase error Θe . So we can write the equation as equation (2.2).
Kd is the gain of the phase detector.
Ud(t) = Kd x Θe (2.2)
ω2
ω0
Uf(t) Figure 2-2 The VCO transfer function
Equation (2.2) is plotted graphically in the Figure 2-3.The output signal Ud (t) of the PD Consists of a dc component and a superimposed ac component.
Loop Filter:
Because the output signal of the PD consists ac component and it is undesired, so we need a loop filter to cancel the ac component.
Different types of PLLs have different building blocks. Following sections will
Figure 2-3 The PD transfer function
2-2 Linear PLL
Although the PLL is a non-linear system, it can be described with a linear model if the loop is in lock. [2.3] When the loop is in lock the phase error signal generates by the phase detector settles on a constant value. In the locked state, the output signal has a fixed frequency as the input reference signal. A phase difference between the input reference signal and output signal may exist depending on the type of PLL used.
When the loop is in lock the phase difference remains constant.
The Linear PLL is built from three purely analog function blocks. They are Phase Detector, Loop Filter and VCO .The three blocks are describe in the following:
PD: PD can be a four phase analog multiplier or analog signal mixer.
LF: LF is a passive or active RC filter, it filter high frequency signal and noise from phase detector and environment. The output of the filter is a DC value to send to VCO.
VCO: It is a ring oscillator which construct by inverters. The frequency is controlled by
the DC value from PD.
Figure 2-4 Linear PLL model
The building blocks of Figure 2-4 are taken as basis for the mathematical model of a
( ) out H s ref
θ
=θ (2.3)
Note that the phase detector sums the input reference phaseΘref ,with the feedback phaseΘfb ,and amplifies the difference with a gain KPD to produce an error voltage Ve (s) ,and Ve(s) equal to:
Ve(s) = KPD x Θe(s) = KPD x [Θref (s)
-
Θout(s)] (2.4)And the output of the loop filter is Vc(s), and Vc(s) equal to:
Vc(s) = Ve(s) x F(s) (2.5)
Because the VCO can be modeled as a phase integrator, the transfer function of the VCO block equal to KVCO/S. So the output of the VCO equal to:
The phase error transfer function is equal to the following:
( ) ( )
The VCO control voltage transfer function is equal to the following:
( ) ( )
The following observation is made from the transfer function give in equation (2.7), (2.8) and (2.9).At first, we discuss the Linear PLL transfer function, give in equation (2.7), it has a low-pass characteristic. This means that for slow (low frequency) variations in the reference phase, the loop will basically track the input signal and produce an output phase.
The phase error transfer function, give in equation (2.8), has a high pass characteristic. This implies that for slow variations in the reference phase, the phase error will be small. However, fast variations in the reference phase will not be filtered and show up as a phase error.
The VCO control voltage transfer function, give in equation (2.9), also has a high pass characteristic. However, depending on the parameter of the loop filter, it can take on a more band-pass shape.
The linear model in Figure 2-4 enables us to analyze the tracking performance of
the responses of the Linear PLL in S-domain, and then, calculate all parameter to design a Linear PLL to satisfy the specification.
2-3 Digital PLL
In this section, we will describe the operating principle and circuit design of Digital PLL. [2.2] Figure 2-5 shows the Digital PLL which consists Digital Phase Frequency Detector, analog Charge Pump, analog Loop Filter, analog Voltage Controlled Oscillator and Frequency Divider.
Figure 2-5 Digital PLL Block
The Phase Frequency Detector can detect the phase and frequency error between the input reference signal and feedback clock signal. The output of the PFD is up signal or down signal. The up signal and down signal control the Charge Pump to
charge or discharge. Loop Filter can filter the high frequency signal. Loop Filter outputs a low frequency signal to control the VCO. By including a Frequency Divider in the feedback path, the VCO output clock runs N times faster than the feedback clock. The next sections will describe the circuit and behavior of the PFD, CP, LP, FD, and VCO.
2-3-1 Phase Frequency Detector
This section will describe the operation and implementation of the PFD circuit.
Figure 2-6 shows an example of the PFD circuit and Figure 2-7 shows the waveforms in some conditions. Unlike multipliers and XOR gate, sequential PFD generates two outputs that are not complementary. Illustrated in Figure 2-6, the operation of a typical PFD is as follows.
Figure 2-6 Phase Frequency Detector Block D Q
produces positive pulses at down signal, while up signal remains at zero.
Conversely, if input reference is high and feedback clock is low then positive pulses appear at up signal while down signal is zero. It should be note that, in principle, up and down are never high together in the simulation. The average value of up – down is an indication of the frequency or phase difference between input reference and feedback clock. [2.2]
Figure 2-7(A) Figure 2-7(B)
Figure 2-7(A) PFD response with input reference lagging feedback clock Figure 2-7(B) PFD response with
ω
reference lagging fω
feedback clockIn the Figure 2-8, it shows the PFD circuit behavior. It has three state diagrams:
up=1,down =0(state I ) ; up=0,down=0(state 0 ) ; up=0,down=1(state II ) ;
Figure 2-8 PFD state diagram
Because the PFD is buildup from two edge-triggered sequential circuits, we can avoid dependence of the output upon the duty cycle of the inputs. If the PFD is in the state 0, up=down=0, then a transition on A take it to state I, where up=1, down=0.
With state I is reached, any more rising edges at input A won’t cause state change at all. The circuit will remain in this state until a transition occurs on B, upon which the PFD returns to state 0. The switching sequence between state 0 and state II is similar.
The PFD can nominally detect a full range of phase difference, i.e. +2π, -2π. A phase difference larger than 2π is truncated with respect to integer of 2π. The output of the PFD can drive a three-state charge pump. The charge pump and loop filter will be discussed followed.
2-3-2 Charge Pump/Loop Filter
In a PLL system, the charge pump transfers the digital signal of up and down
pump circuit. It consists of both matched current sources, each with a fixed value.
When the up signal is high, the switch connects to A and Vc is charged by the up current source Iup. Similarly, when the down signal is high, the switch connects to B and Vc is charged by the lower current source Idown. If both up signal and down signal are low, then the switch maintains at original node and Vc holds the original voltage.
Most of the PLL’s specifications are determined by the loop filter. The loop filter can be either passive or active. In general, a passive filter is simple to design and has better noise performance. The passive filter was shown in Figure 2-10, which may be first-order, second-order, or other high order structures.
As show in Figure 2-11, charge pump circuit convert the logic state of the PFD (Up and Down) into an analog counterpart for controlling the VCO. The charge pump output and the input of a VCO must have the low leakage tendency. So a passive loop filter shapes the output of the charge pump circuit to suppress the un-wanted message.
The time domain response can be shown in Figure 2-11.
As discussed in the previous section, if the input reference signal leads the feedback signal, the pulse appear at up signal, then positive charge accumulates on capacitor steadily.
Conversely, if the input reference signal lags the feedback signal, the charge is removed from capacitor on every phase comparison. In the third state, when input reference and feedback signal are equal, up and down keep low. Both switches are off, and the output signal Vc remains constant.
Figure 2-9 Charge Pump & Loop Filter
ie ie ie
Vc Vc Vc
R1 R1
R2
C
C1
C2
C1
C2 C3
(A) (B) (C)
Figure 2-10 Loop Filter
Figure 2-11 The response of charge PFD & pump & Loop Filter
The above discussions of the Figure 2-11 only use a capacitor as the loop filter.
But this kind of filter makes the PLL unstable. We can use the loop filter which was shown in Figure 2-10(B), Figure 2-10(C) to avoid instability.
2-3-3 Voltage Controlled Oscillator
In this section, we will describe the voltage-controlled oscillator which is the critical circuit in the PLL. The input voltage of the VCO generated from the loop filter and the output frequency signal of VCO is controlled by the input voltage. In some oscillators, the frequency of the oscillator is controlled by a current rather then a voltage.
They are referred as current-controlled oscillators (CCO) and play the same role as those of VCOs in PLLs. The VCO and CCO are similar. Of course, there are various types of VCO than can be used in PLLs. The Table 2-1 show three various types of VCO. Basically, the VCO has to fulfill some constraints is the phase noise in the frequency domain or the timing jitter in the time domain. Other important factors are the bandwidth of the VCO, linearity of the controlled voltage, output voltage swing and the power consumption.[2.4][2.5][2.6]
Type Advantage Disadvantage
Voltage controlled crystal oscillators
Phase accuracy, good noise performance
Cannot be integrated and cost is high and low
frequency Ring oscillator VCOs Suitable for integration
and have wide control range
Poor jitter performance
LC-tuned oscillators High frequency and good noise performance
The inductor is difficult to integrate and cost high
Table 2-1 The advantage and disadvantage of different type oscillators
Some of the most important considerations of VCO are: [2.7]
(1)Phase Stability:
The frequency spectrum of a VCO output should look likes an ideal impulse, i.e., the phase noise of a VCO must be as low as possible.
(2)Electrical Tuning Range:
The tunable frequency range of a VCO must be able to cover the entire required frequency range of the interested application.
(3) Tuning Linearity:
An ideal VCO has a constant gain at the entire frequency range. Also, a constant VCO gain can simplifies the design procedure of a VCO.
(4) Power Supply Sensitivity:
Since there are many digital circuits in a modern transceiver circuit, the switching activities of digital circuits will somewhat influence the power supply of the whole system. The switching noise induced by digital circuits will also couple to the power supply of the VCO and influence its output waveform. Therefore, in VCO the dependency of the oscillating frequency on the power supply must be as low as possible.
(5) Frequency pushing:
The dependency of the center frequency on the power supply voltage.
(6) Frequency pulling:
The dependency of the center frequency on the output load impendence.
(7) Low cost, Phase noise, DC consumption current, Harmonic/spurious
gm
L
Rc Rp
RL
Vout
Figure 2-12 LC-Tank Voltage-Controlled Oscillator
In the next, we will show an LC-Tank VCO, relaxation oscillator and ring oscillator in the Figure 2-12, Figure 2-13 and Figure 2-17. [2.6] In the LC-Tank VCO, the oscillation conditions are already shown by [2.6]. Where RP is the parasitic resistance in parallel to the LC-tank, and RL and RC are the parasitic resistances of L and C, respectively.
0
1
ω =
L C (2.10)e
0
2
R 1
( )
ff c L
P
R R
R ω C
= + +
⋅
(2.11)Figure 2-13 Five stage signal ended ring oscillator
The second type oscillator is ring oscillator as shown in Figure 2-13 has been widely used in PLL for application of clock recovery and clock generation before and Figure 2-14 shows the detail circuit of the Figure 2-13.
A ring oscillator can be smoothly integrated in a standard CMOS process without taking extra processing steps because it dose not require any passive resonant element.
Figure 2-14 Detail five stages circuit in Figure 2-13
When the ring oscillator is employed as a voltage controlled oscillator, the desired wide operating frequency range can be easily obtained. Different output frequency is achieved by adjusting the timing delay of each stage in the ring oscillator.
Figure 2-15 Differential Ring Oscillator
Also, there is another type of ring oscillator, differential ring oscillator, as shown in Figure 2-15.The detail circuit of Figure 2-15 show in the Figure 2-16.
Figure 2-16 The circuit of each stage in Figure 2-15
The third type oscillator is the relaxation oscillator, it shows in the Figure 2-17.
The relaxation oscillator is also known as multivibrator, incorporating hysteresis characteristics that can oscillate even with a small phase shift. The relaxation oscillator and ring oscillator utilize the positive feedback characteristics and are known as resonatorless oscillators. [2.8]
The other category of oscillator is to eliminate that the real part of the loop’s impedance so that the poles are pure imaginary. The LC-tank VCO is a typical resonator oscillator that bases on the idea and is called resonator oscillator. The VCO is the most challenging part of the PLL and we have to design carefully.
R1 R2
M 1 M 2
C1
I I
Figure 2-17 The relaxation oscillator
2-3-4 Frequency Divider
In some application, we need a high frequency clock generator and the crystal-oscillator is not satisfied, because the frequency of the crystal-oscillator is too small. Therefore, the multiple-frequency-technology that utilizes PLL is presented.
For example, the divider module is four. The output frequency of VCO is a four times of the input reference signal’s frequency, i.e.,
o u t in
f = N f
,N = 4
(2.13)=
The Figure 2-18 show an example of divider, it uses a TSPC register. The next is the advantages and the disadvantages of the divider:
Advantages:
Reasonably fast
No static power consumption Compact size
Differential clock not require
Disadvantages:
Slowed down by stacked PMOS, signals goes through three gates per cycle Requires full swing input clock signal
Figure 2-18 Divide-by-2 using a TSPC register
If we need higher division, it can be achieved by simple cascading divide-by-2 stages.
The Figure 2-19 shows a divider (1/4) waveform.
Figure 2-19 A divider (1/4) waveform
2-4 All Digital PLL
Figure 2-20 All Digital Phase-Locked Loop
In this section we will describe All Digital PLL, it has characteristics of fast
applications today. The ADPLL is made as a digital building block, it dose not contain any passive component, such as resistors and capacitors.
The ADPLL consists of a digital phase frequency detector (PFD), a control unit, a frequency divider, and digital control oscillator (DCO) as show in Figure 2-20. All signals in the ADPLL are digital signals. The PFD detects the frequency difference and the phase difference between the input reference signal and the feedback signal.
The control unit receives the signal, produced by the PFD, and produces a set of digitally controlled signals to control the DCO.
By including a divide-by-N divider in the feedback path, the DCO output frequency runs N times faster than input reference signal. The divided-by-N divider is an optional component in the ADPLL. The functional blocks of the ADPLL imitate the function of the corresponding analog blocks. Because the ADPLL consists of digital circuits entirely, there are many different of design methods to achieve the functions of them.
The ADPLL system is a discrete-time system, hence analyzing the ADPLL in s-domain is not suitable. Although it is possible to take an entire PLL-description and then transform it from s-domain into z-domain, this is unnecessary difficult. Instead, one transforms each component into z-domain and then proceeds with the analysis in z-domain. The ADPLL is best described in z-domain.
In the Linear PLL, Digital PLL and All Digital PLL, they have many advantages and disadvantages respectively. We compare and illustrate them in Table 2-2.As show in the Table 2-2, we can know they use different design methodology, because the
ADPLL is a digital circuit design so it can be designed by standard cell library.
ADPLL is a digital circuit design so it can be designed by standard cell library.