超低功率高面積使用率全數位鎖相迴路頻率合成器

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(1)國立交通大學電子工程學系電子研究所碩士班碩士論文. 超低功率高面積使用率全數位鎖相迴路頻率合成器 Ultra Low Power Area Efficient All Digital Phase-Locked Loop Frequency Synthesizer. 研究生：陳冠華指導教授：黃. 威. 教授. 中華民國九十五年九月.

(2) 超低功率高面積使用率全數位鎖相迴路頻率合成器 Ultra Low Power Area Efficient All Digital Phase-Locked Loop Frequency Synthesizer 研究生：陳冠華. Student：Kwan-Hwa Chen. 指導教授：黃. Advisor：Prof. Wei Hwang. 威教授. 國立交通大學電子工程學系電子研究所碩士論文. A Thesis Submitted to Department of Electronics Engineering & Institute of Electronics College of Electrical and Computer Engineering National Chiao Tung University in Partial Fulfillment of the Requirements for the Degree of Master in Electronics Engineering September 2006 Hsinchu, Taiwan, Republic of China. 中華民國九十五年九月.

(3) 超低功率高面積使用率全數位鎖相迴路頻率合成器. 學生：陳冠華. 指導教授：黃威教授. 國立交通大學電子工程學系電子研究所碩士班. 摘. 要. 本論文提出一個運用所提出的低功率演算法的全新全數位鎖相迴路架構。低功率的搜尋演算法能使我們的全數位鎖相迴路在 22 個參考週期內完成相位鎖定，而且可以使硬體方面簡單及面積小的優點。並且在論文中提出的低功率數位控制震盪器具有兩種架構，第一種適合用在高速下，而第二種適合用在寬的頻率範圍。這兩種數位控制震盪器都可以使全數位鎖相迴路更加地省電。提出的邏輯及閘鎖存器為基礎的頻率相位偵測器可以偵測多種參考頻率的倍數。總體而言，我們所提出的全數位鎖相迴路具有面積小以及低功率消耗的特性。本論文以TSMC 0.13um 1P8M CMOS 技術實現。供給電壓為 1.2 伏，總面 2. 積為 0.0041mm 。模擬結果顯示當數位控制震盪器頻率為 700 萬赫茲時，全數位鎖相迴路的相位抖動為 18.4ps,1.38%(Pk-Pk)，而總功率消耗為 0.85mW。 i.

(4) Ultra Low Power Area Efficient All Digital Phase-Locked Loop Frequency Synthesizer. Advisor：Prof. Wei Hwang. Student：Kwan-Hwa Chen. Department of Electronics Engineering & Institute of Electronics National Chiao-Tung University. ABSTRACT. A new all digital phase-locked loop (ADPLL) architecture with low power algorithm is presented in this thesis. The proposed low power search algorithm can accomplish phase lock process within 22 input clock cycles and make the hardware simple, area small. In thesis, proposed low power digitally controlled oscillator (DCO) has two types. The two types of proposed DCO make proposed ADPLL. lower. power.. The. proposed. NAND. latch. based. Phase-Frequency-Detector (PFD) can detect multi times of reference frequency .This ADPLL has characteristics of small area cost and lower power consumption.. The proposed ADPLL is simulated and implemented by TSMC 0.13um 1P8M CMOS technology. The supply voltage is 1.2v and total area is 0.0041mm2. The simulation results show that when the DCO operates at. ii.

(5) 700MHz, the jitter is 18.4ps, 1.38% (Pk-Pk) and the total power consumption of ADPLL is 0.85mW.. iii.

(6) Acknowledgements I would like to express my deepest gratitude to my advisor Prof. Wei Hwang for his enthusiastic guidance and encouragement throughout the research. With his support, I have the confidence and energy to stride forward.. Following, I would like to thank all my friends, Po-Tsang Huang, Ming-Hung Jang, Hau-Yi Yang, Chung-Hsien Hua, Wei-Jr Shie, Jang-Shiuan Jang, Jung-Wen Liou, Shu-Wei Jang, and Tzung-Shi Yang, at LPSOC lab. They provide an interesting place for life and work and also gave me much support and discussion on my thesis research.. Finally, I give the greatest respect and love to my father Yung-Jang Chen, my mother Su-Chiung. Huang, sister Yi-Jie Chen, big brother Tzai-Ting Chen, little brother Jiu-Yu Chen,. my room-mate Jian-Ming Huang, Shr-Fen Jang, Shr-Ling Jjang and my girl friend Shr-Han Jang. I want to express my highest appreciation for their support and understanding.. iv.

(7) Table of Contents 摘要............................................................................................................... i Abstract.........................................................................................................ii Acknowledgments…………………………..............................................................................iv Table of Contents.........................................................................................................v List of Tables ...............................................................................................vii List of Figures................................................................................................viii Chapter 1 Introduction ……………………………………….…………………1 1-1 Research motivation……………………………………………………………….…1 1-2 Thesis organization…………………………………………………………………4. Chapter 2 PLL Overview ………………………………………….…………………5 2-1 The operating principle of PLL....................................................................…5 2-2 Linear PLL........................................................................................................9 2-3 Digital PLL.......................................................................................................13 2-3-1 Phase Frequency Detector.....................................................................14 2-3-2 Charge Pump/Loop Filter......................................................................16 2-3-3 Voltage Controlled Oscillator...............................................................19 2-3-4 Frequency Divider ................................................................................26 2-4 All Digital PLL.................................................................................................28. Chapter 3 Proposed Low Power Digitally Controlled Oscillator .................33 3-1 Basic Concepts of Digitally Controlled Oscillator…………………………………...33 3-2 Digitally Controlled Oscillator(DCO)…………………….…………………………….34 3-3 Low power Digitally Controlled Oscillator ....................................................46. v.

(8) Chapter 4 Proposed All Digital Phase-Locked Loop (ADPLL) ...........................65 4-1 Conventional ADPLL …………………………………............................................65 4-2 The Algorithm of Proposed ADPLL………………… ..................................................71 4-3 The Architecture of Proposed ADPLL .................................................................75 4-5 Phase Frequency Detector.....................................................................................78 4-5 DCO Enable Generator Design / Control Unit.........................................................83. Chapter 5 Application and Simulation result……….....................................87 5-1 Application...............................................................................................87 5-2 Simulation Result................................................. ...................................88 5-3 Layout Implementation......................................... ...................................93. Chapter 6 Conclusion and Future Work........................................................97 6-1 Conclusion......................................................................................................97 6-2 Future Work..........................................................................................99 Reference..............................................................................................102. vi.

(9) List of Tables Table 2-1. The advantage and disadvantage of different type oscillators…………20. Table 2-2. The advantage and disadvantage of different type PLL………………….30. Table 2-3. Design issues of ADPLL................………………………………………32. Table 3-1. Transmission gate simulation with different size ….…………..…..51. Table 3-2. The increment of Type-1 with and without shunt …..……………….….60. Table 3-3. The increment of Type-2 with and without shunt ……………...….…60. Table 3-4. comparison with existing DCO………………………………….. …….64. Table 6-1. The summary of our ADPLL………………………………………..…98. Table 6-2. Performance comparison of all-digital clock generator…………..….99. vii.

(10) List of Figures. Figure 1-1(A). Clock Tree & Clock skew....................................................…………1. Figure 1-1(B). PLL for clock de-skewing application..................................................2. Figure 1-2. PLL for frequency synthesizer application...........................................2. Figure 1-3. PLL for Clock Data Recovery application..........................................3. Figure 2-1. Block diagram of PLL..........................................................................6. Figure 2-2. The VCO transfer function.........................................................…..…8. Figure 2-3. The PD transfer function.........................................................……….9. Figure 2-4. Linear PLL model....................................................................……….10. Figure 2-5. Digital PLL Block......................................................................…….13. Figure 2-6. Phase Frequency Detector Block ...............................................…..14. Figure 2-7(A). PFD response with input reference lagging feedback clock....……15. Figure 2-7(B). PFD response with. Figure 2-8. PFD state diagram..................................................................………16. Figure 2-9. Charge Pump & Loop Filter.......................................………………18. Figure 2-10. Loop Filter............................................................................………..18. Figure 2-11. The response of charge PFD & pump & Loop Filter………………19. Figure 2-12. LC-Tank Voltage-Controlled Oscillator....................................……22. Figure 2-13. Five stage signal ended ring oscillator....................................……23. Figure 2-14. Detail five stages circuit in Figure 2-13....................................……23. Figure 2-15. Differential Ring Oscillator....................................…………………24. Figure 2-16. The circuit of each stage in Figure 2-16....................................…….25. Figure 2-17. The relaxation oscillator.....................................................................26. Figure 2-18. Divide-by-2 using a TSPC register....................................…….…27. Figure 2-19. A divider (1/4) waveform....................................………………….28. ω reference lagging f ω feedback clock ..................15. viii.

(11) Figure 2-20. All Digital Phase Locked-Loop....................................……………..28. Figure 3-1. Digitally Controlled Oscillator [3.1]……….…………...…………….35. Figure 3-2. The DCO cell [3.1]…………………………………………………….36. Figure 3-3. Another delay element [3.6]…………………...………………………37. Figure 3-4(A). DCO consisting of 14 D/A converters and a current-starved inverter VCO [3.4] ….....……………………………………………………………..….39. Figure 3-4(B). DCO consisting of 14 D/A converters and a current-starved inverter VCO [3.4]……………………………………………………………40. Figure 3-5. Simulated period time versus digital control word W for the DCO of Figure 3-12 [3.4]………………………………………………………………….40. Figure 3-6. Schematic diagram of a 4 bits DCO [3.5] ..……..……..……….……41. Figure 3-7. A multiple path selection DCO [3.2]…………………….…………….43. Figure 3-8. Numerically controlled oscillator [3.3]……………………..…………….43. Figure 3-9. The simulated period time V.S. digital controlled word in Figure 3-8…44. Figure 3-10. Structure of DCO in [3.7]………………………………………………….45. Figure 3-11(a). five stages inverter oscillator……………………….…………….…..….46. Figure 3-11(b). turn on transmission gate…………….……………………….……….…47. Figure 3-12. Simulated equivalent resistance of transmission gate for low-to-high transition (for (W/L)n = (W/L)p = 0.5mm/0.25mm)……………………49. Figure 3-13(a). A chain of transmission gates…………………………………………….52. Figure 3-13(b). Equivalent RC network………………………………………….………....52. Figure 3-14(a). Type-1 DCO……………………………………………………………...…53. Figure 3-14(b). Type-2 DCO………………………………………………………..…….…53. Figure 3-15(a). Type-1 shunt transmission gate…………………………………………….55. Figure 3-15(b) Path 1 (AE) equivalent circuit…………………………………………….55 Figure 3-15(c) Path 2 (ADE) equivalent circuit………………………………………….55 Figure 3-15(d) Path 3 (ACDE) equivalent circuit…………………………………….…..55 ix.

(12) Figure 3-15(e) Path 4 (ABCDE) equivalent circuit………………………………………...56 Figure 3-16(a). Type-2 shunt transmission gate……………………………………………..57. Figure 3-16(b) Path 1 (CE) equivalent circuit……………………………………………57 Figure 3-16(c) Path 2 (CDE) equivalent circuit………………………………………….58 Figure 3-16(d) Path 3 (BCDE) equivalent circuit………………………………………..58 Figure 3-16(e). Path 4 (ABCDE) equivalent circuit…………………………………….58. Figure 3-17(a). Type-1 DCO……………………………………………………………...61. Figure 3-17(b). Type-2 DCO……………………………………………………………..61. Figure 3-18. Type-1 DCO and Type-2 DCO simulation………………………..62. Figure 3-19. Path-8 Type-2 DCO simulation…………………………………….63. Figure 3-20. Fine Tune Cell simulaton………………………………………….63. Figure 4-1. The flow chart of the frequency acquisition mode………...66. Figure 4-2. Modified binary search(Frequency acquisition)………..….67. Figure 4-3. The flow chart of the phase acquisition mode…………….68. Figure 4- 4. Conventional ADPLL block dia gra m [2.9]………………..69. Figure 4-5. Binary Search……………………………………………….….72. Figure 4-6. Low power binary Search…………………………………….73. Figure 4-7(a). Binary Search…………………………………………………...74. Figure 4-7(b). Low power binary search…………………………………....74. Figure 4-8. architecture of proposed ADPLL……………………..….76. Figure 4-9. flow chart of the proposed low power binary searc.78. Figure 4-10. proposed phase frequency detector……………………..79. F i g u r e 4 - 11. the waveform of PFD multiplier signal up/down/lock...80. Figure 4-12. the waveform of PFD NAND latch signal up/down.…80. Figure 4-13. D-Flip-Flop……………………………………………………81. Figure 4-14. modified low power digitally control oscillator……..82. x.

(13) Figure 4-15. DCO Enable signal for the first rising edge aligning (ADPLL locked)……………………………..……83. Figure 4-16. DCO Enable signal for the first rising edge aligning (ADPLL not yet locked)………………………………84. Figure 4-17. Div2 & DCO enable generator…………………………85. Figure 4-18. PFD enable generator…………………………….………86. Figure 4-19. DCO word value decision…………………………..….86. Figure 5-1. Block diagram of the frequency synthesizer….88. Figure 5-2(A). The locked process waveform of 700Mhz ADPLL (TT corner)….90. Figure 5-2(B). The locked state waveform of 700Mhz ADPLL (TT corner)…....90. Figure 5-3(A). The locked process waveform of 700Mhz ADPLL (SS corner)...91. Figure 5-3(B). The locked state waveform of 700Mhz ADPLL (SS corner)…....91. Figure 5-4(A). The locked process waveform of 800Mhz ADPLL….....................92. Figure 5-4(B). The locked state waveform of 800Mhz ADPLL ……………...….93. Figure 5-5. Floor planning of ADPLL……………………….….94. Figure 5-6. The layout of ADPLL……………………………......95. Figure 5-7. Area result of ADPLL layout………………………96. Figure 6-1. QDR interface chip[6.6]………………………...….101. xi.

(14) Chapter 1 Introduction 1-1 Research motivation The phase-locked loop (PLL) has been widely used in consumer, computer and communication aspects. It performs the tasks of frequency synthesis, clock / data recovery, clock de-skewing, duty-cycle enhancement and so on [1.1]. Now we show some applications of PLL.. 1) PLL for clock de-skewing application As shows in Figure 1-1(A), the skew between point A (or point B) and clock_in is due to the clock tree. Figure 1-1(B) shows the PLL application of clock de-skewing, skew between clock_in and point A (or point B) can be eliminated, even when there are delay differences between the two paths due to clock buffering and other factors.. Clock_in. Clock_in. A or B. Clock skew. A. B. Figure 1-1(A) Clock Tree & Clock skew. 1.

(15) A or B. Clock_in PFD. CP/LPF. VCO. Figure 1-1(B) PLL for clock de-skewing application. 2) PLL for frequency synthesizer application As shows in Figure 1-2, the PLL is used as a frequency synthesis to generate a synthesized clock. The output frequency of F_out clock is synthesized as. F_out = ( M / N ) x F_in. (1.1). A frequency synthesizer allows the designer to generate a variety of output frequencies as multiples of a single reference frequency. The main application is in generating local oscillator (LO) signals for the up- and down-conversion of RF signals.. F_in. Divider M. F_out PFD. CP/LPF. Divider N. Figure 1-2 PLL for frequency synthesizer application. 3) PLL for Clock Data Recovery application 2. VCO.

(16) As shows in Figure1-3, it is the PLL application for Clock Data Recovery (CDR). In general, the task of the Clock Data Recovery architectures is to recovery the phase-and-frequency information from the input by extracting the clock from transitions in the data stream.. Data in. Data out Decision circuit. PFD. CP/LPF. VCO. Recovery clock. Figure 1-3 PLL for Clock Data Recovery application. Traditionally, a PLL is made as an analog building block. However, integrating an analog PLL in a digital noisy system-on-chip (SoC) environment is difficult. In addition, the analog PLL is sensitive to process parameters and must be redesigned for each new technology. Assuming that the digitally controlled PLL is implemented with only active components such as transistors, it will scale with technology. Capacitors and resistors, which are used in analog circuits will not scale with technology to the same extent [1.2][1.3].. If we integrate an analog circuit with digital circuit, the digital noise affects the performance of the analog circuit. It is difficult to isolate the noise which generated from the digital part. Also, in the IC process, the digital process is usually different from the analog process. In analog PLL, we must pay more attention to the matching problem and provide good quality of capacitor.. The Since the implementation of analog component in a digital environment is not a simple task, the linear phase-locked loop (LPLL) and classical digital phase-locked 3.

(17) loop (DPLL) which relay on analog component have been replaced by the all digital phase-locked loop (ADPLL). The ADPLL becomes more and more popular in recently year. It can avoid the disadvantages of analog circuits by using the ADPLL in digital system. Also, the ADPLL has characteristics of fast frequency locking, full digitization, and good stability.. 1-2 Thesis organization This thesis is organized as below. . Chapter 1 Introduction. . Chapter 2 PLL overview. . Chapter 3 Proposed Low Power Digitally Controlled Oscillator (DCO). . Chapter 4 Proposed Low Power All Digital Phase-Locked Loop. . Chapter 5 Application and Simulation Result. . Chapter 6 Conclusion and Future Work. Chapter 2 PLL overview We give the overview of phase-locked loop (PLL), including LPLL, DPLL and ADPLL. Chapter 3 Proposed Low Power Digitally Controlled Oscillator (DCO) We introduce many kinds of digitally controlled oscillator and propose the low power digitally control oscillator. Chapter 4 Proposed Low Power ALL Digitally Phase-Locked Loop (ADPLL) We introduce the algorithm and architecture of conventional ADPLL which is proposed by Motorola in 1995. And, We present a low power search algorithm and multi-time phase frequency detector and state the circuit design in each function block such as control unit, enable generator match delay line.. Chapter 5 Application and simulation result Chapter 6 Conclusion and Future Work. 4.

(18) Chapter 2. PLL overview. In this chapter, we will review three kinds of phase locked-loop circuit [2.1], they are: Linear PLL (LPLL), Digital PLL (DPLL), and All-Digital PLL (ADPLL). The very first phase locked-loops (PLLs) were implemented as early as 1932 by de Bellescize; this French engineer considered the inventor of coherent communication. The PLL found broader industrial applications only when it becomes available as an integrated circuit.. The first PLL ICs appeared around 1965 and were purely analog devices. In the following years the PLL drifted slowly but steadily into digital territory. The very first digital PLL (DPLL), which appeared around 1970, was in effect a hybrid device. A few years later, the all-digital PLL (ADPLL) was invented. The ADPLL is exclusively built from digital function blocks and hence do not contain any passive components like resistor and capacitors. Different types of PLLs behave differently.. Classifications of PLL circuit. (1) LPLL: Linear PLL. Each block is analog.. (2) DPLL: Digital PLL. Phase Detector is digital and the others are analog.. (3) ADPLL: All Digital PLL. Each block is digital. Loop filter is from Up/Down counter. VCO (Voltage Controlled Oscillator) is from DCO (Digital Controlled Oscillator).. 5.

(19) 2-1. The operating principle of PLL A PLL is a circuit which causes a particular system to track with another one.. More precisely, a PLL is a circuit synchronizing an output signal (generate by an oscillator) with a reference or input signal in frequency as well as in phase. In the synchronized—often called locked—state the phase error between the oscillator’s output signal and the reference signal is zero, or very small. If phase builds up, a control mechanism acts on the oscillator in such a way then the phase error is again reduced to a minimum. In such a control system the phase of the output signal is actually locked to the phase of the reference signal. This is why it is referred to as a phase-locked loop. The operating principle of the PLL is explained by the example of the linear PLL. [2.2]. Figure 2-1 Block diagram of the PLL. 6.

(20) In the Figure 2-1, the signals of interest within the PLL circuit are defined as follows:. U1(t):. the reference(or input ) signal. ω1:. the angular frequency of the reference signal. U2(t): the output signal of the VCO ω2 :. the angular frequency of the output signal. Ud(t): the output signal of the detector Uf(t):. the output signal of the loop filter. Θe:. the phase error define as the phase difference between signals U1(t) and U2(t). Now we look at the operations of the three functional blocks in the Figure 2-1.. Functional Blocks： VCO: VCO generate an angular frequency ω2 ,which is determined by the output signal Uf of the loop filter. The angular frequency ω2 is given by equation (2.1) , where ω 0 is the center frequency of the VCO and the K0 is the VCO gain. Equation2.1 is plotted graphically in the Figure 2-2.. ω2 =ω0 + K0 x Uf(t). (2.1). Phase Detector: the Phase Detector compares the phase of the output signal of VCO with the phase of reference signal and generate an output signal Ud(t) which is approximately. 7.

(21) proportional to the phase error Θe . So we can write the equation as equation (2.2). Kd is the gain of the phase detector.. Ud(t) = Kd x Θe. (2.2). ω2. ω0. Uf(t). Figure 2-2 The VCO transfer function. Equation (2.2) is plotted graphically in the Figure 2-3.The output signal Ud (t) of the PD Consists of a dc component and a superimposed ac component.. Loop Filter: Because the output signal of the PD consists ac component and it is undesired, so we need a loop filter to cancel the ac component.. Different types of PLLs have different building blocks. Following sections will discuss Linear PLL, Digital PLL and All Digital PLL The next section will analyze and design Linear PLL. 8.

(22) Figure 2-3 The PD transfer function. 2-2 Linear PLL Although the PLL is a non-linear system, it can be described with a linear model if the loop is in lock. [2.3] When the loop is in lock the phase error signal generates by the phase detector settles on a constant value. In the locked state, the output signal has a fixed frequency as the input reference signal. A phase difference between the input reference signal and output signal may exist depending on the type of PLL used. When the loop is in lock the phase difference remains constant. 9.

(23) The Linear PLL is built from three purely analog function blocks. They are Phase Detector, Loop Filter and VCO .The three blocks are describe in the following:. PD: PD can be a four phase analog multiplier or analog signal mixer. LF: LF is a passive or active RC filter, it filter high frequency signal and noise from phase detector and environment. The output of the filter is a DC value to send to VCO. VCO: It is a ring oscillator which construct by inverters. The frequency is controlled by the DC value from PD.. Figure 2-4 Linear PLL model. The building blocks of Figure 2-4 are taken as basis for the mathematical model of a Linear PLL in lock. The following analysis shows step by step how to obtain the Linear PLL transfer function. The next is the transfer function: 10.

(24) H ( s) =. θ out θ ref. (2.3). Note that the phase detector sums the input reference phaseΘref ,with the feedback phaseΘfb ,and amplifies the difference with a gain KPD to produce an error voltage Ve (s) ,and Ve(s) equal to:. Ve(s) = KPD x Θe(s) = KPD x. [Θref (s) - Θout(s)]. (2.4). And the output of the loop filter is Vc(s), and Vc(s) equal to:. Vc(s) = Ve(s). x. F(s). (2.5). Because the VCO can be modeled as a phase integrator, the transfer function of the VCO block equal to KVCO/S. So the output of the VCO equal to:. θ out ( S ) =. Vc(S) x Kvco S. So the transfer function of the Linear PLL H(S), is equal to the following:. H (S ) =. θ out ( S ) KPDKVCOF ( S ) = θ ref ( S ) S + KPDKVCOF ( S ). (2.7). The phase error transfer function is equal to the following: 11. (2.6).

(25) H (S ) =. θ e( S ) S = θ ref ( S ) S + KPDKVCOF ( S ). (2.8). The VCO control voltage transfer function is equal to the following:. H (S ) =. VC ( S ) SKPDF ( S ) = Vref ( S ) S + KPDKVCOF ( S ). (2.9). The following observation is made from the transfer function give in equation (2.7), (2.8) and (2.9).At first, we discuss the Linear PLL transfer function, give in equation (2.7), it has a low-pass characteristic. This means that for slow (low frequency) variations in the reference phase, the loop will basically track the input signal and produce an output phase.. The phase error transfer function, give in equation (2.8), has a high pass characteristic. This implies that for slow variations in the reference phase, the phase error will be small. However, fast variations in the reference phase will not be filtered and show up as a phase error.. The VCO control voltage transfer function, give in equation (2.9), also has a high pass characteristic. However, depending on the parameter of the loop filter, it can take on a more band-pass shape.. The linear model in Figure 2-4 enables us to analyze the tracking performance of the Linear PLL, i.e., the system maintains phase tracking when excited by phase steps, frequency steps, or other excitation signals. So we can analyze the characteristic and 12.

(26) the responses of the Linear PLL in S-domain, and then, calculate all parameter to design a Linear PLL to satisfy the specification.. 2-3 Digital PLL In this section, we will describe the operating principle and circuit design of Digital PLL. [2.2] Figure 2-5 shows the Digital PLL which consists Digital Phase Frequency Detector, analog Charge Pump, analog Loop Filter, analog Voltage Controlled Oscillator and Frequency Divider.. Figure 2-5 Digital PLL Block. The Phase Frequency Detector can detect the phase and frequency error between the input reference signal and feedback clock signal. The output of the PFD is up signal or down signal. The up signal and down signal control the Charge Pump to. 13.

(27) charge or discharge. Loop Filter can filter the high frequency signal. Loop Filter outputs a low frequency signal to control the VCO. By including a Frequency Divider in the feedback path, the VCO output clock runs N times faster than the feedback clock. The next sections will describe the circuit and behavior of the PFD, CP, LP, FD, and VCO.. 2-3-1 Phase Frequency Detector. This section will describe the operation and implementation of the PFD circuit. Figure 2-6 shows an example of the PFD circuit and Figure 2-7 shows the waveforms in some conditions. Unlike multipliers and XOR gate, sequential PFD generates two outputs that are not complementary. Illustrated in Figure 2-6, the operation of a typical PFD is as follows.. High input reference. D clk. up. Q DFF reset NAND. . High feedback clock. D clk. reset DFF Q. down. Figure 2-6 Phase Frequency Detector Block. When the feedback clock is high and the input reference is low, then the PFD 14.

(28) produces positive pulses at down signal, while up signal remains at zero.. Conversely, if input reference is high and feedback clock is low then positive pulses appear at up signal while down signal is zero. It should be note that, in principle, up and down are never high together in the simulation. The average value of up – down is an indication of the frequency or phase difference between input reference and feedback clock. [2.2]. Figure 2-7(A). Figure 2-7(B). Figure 2-7(A) PFD response with input reference lagging feedback clock Figure 2-7(B) PFD response with. ω reference lagging f ω feedback clock. In the Figure 2-8, it shows the PFD circuit behavior. It has three state diagrams: up=1,down =0(state I ) ; up=0,down=0(state 0 ) ; up=0,down=1(state II ) ;. 15.

(29) Figure 2-8 PFD state diagram. Because the PFD is buildup from two edge-triggered sequential circuits, we can avoid dependence of the output upon the duty cycle of the inputs. If the PFD is in the state 0, up=down=0, then a transition on A take it to state I, where up=1, down=0.. With state I is reached, any more rising edges at input A won’t cause state change at all. The circuit will remain in this state until a transition occurs on B, upon which the PFD returns to state 0. The switching sequence between state 0 and state II is similar.. The PFD can nominally detect a full range of phase difference, i.e. +2π, -2π. A phase difference larger than 2π is truncated with respect to integer of 2π. The output of the PFD can drive a three-state charge pump. The charge pump and loop filter will be discussed followed.. 2-3-2 Charge Pump/Loop Filter. In a PLL system, the charge pump transfers the digital signal of up and down from the PFD to an analog signal. Figure 2-9 shows a simple model of the charge. 16.

(30) pump circuit. It consists of both matched current sources, each with a fixed value. When the up signal is high, the switch connects to A and Vc is charged by the up current source Iup. Similarly, when the down signal is high, the switch connects to B and Vc is charged by the lower current source Idown. If both up signal and down signal are low, then the switch maintains at original node and Vc holds the original voltage.. Most of the PLL’s specifications are determined by the loop filter. The loop filter can be either passive or active. In general, a passive filter is simple to design and has better noise performance. The passive filter was shown in Figure 2-10, which may be first-order, second-order, or other high order structures.. As show in Figure 2-11, charge pump circuit convert the logic state of the PFD (Up and Down) into an analog counterpart for controlling the VCO. The charge pump output and the input of a VCO must have the low leakage tendency. So a passive loop filter shapes the output of the charge pump circuit to suppress the un-wanted message. The time domain response can be shown in Figure 2-11.. As discussed in the previous section, if the input reference signal leads the feedback signal, the pulse appear at up signal, then positive charge accumulates on capacitor steadily.. Conversely, if the input reference signal lags the feedback signal, the charge is removed from capacitor on every phase comparison. In the third state, when input reference and feedback signal are equal, up and down keep low. Both switches are off, and the output signal Vc remains constant. 17.

(31) Figure 2-9 Charge Pump & Loop Filter. ie. Vc. ie. C2. C2. C1. (A). Vc. R1. R1 C. R2. ie. Vc. C3. C1. (B). (C). Figure 2-10 Loop Filter. 18.

(32) Figure 2-11 The response of charge PFD & pump & Loop Filter. The above discussions of the Figure 2-11 only use a capacitor as the loop filter. But this kind of filter makes the PLL unstable. We can use the loop filter which was shown in Figure 2-10(B), Figure 2-10(C) to avoid instability.. 2-3-3 Voltage Controlled Oscillator. In this section, we will describe the voltage-controlled oscillator which is the critical circuit in the PLL. The input voltage of the VCO generated from the loop filter and the output frequency signal of VCO is controlled by the input voltage. In some oscillators, the frequency of the oscillator is controlled by a current rather then a voltage.. 19.

(33) They are referred as current-controlled oscillators (CCO) and play the same role as those of VCOs in PLLs. The VCO and CCO are similar. Of course, there are various types of VCO than can be used in PLLs. The Table 2-1 show three various types of VCO. Basically, the VCO has to fulfill some constraints is the phase noise in the frequency domain or the timing jitter in the time domain. Other important factors are the bandwidth of the VCO, linearity of the controlled voltage, output voltage swing and the power consumption.[2.4][2.5][2.6]. Type. Advantage. Disadvantage. Voltage controlled crystal. Phase accuracy, good. Cannot be integrated and. oscillators. noise performance. cost is high and low frequency. Ring oscillator VCOs. Suitable for integration. Poor jitter performance. and have wide control range LC-tuned oscillators. High frequency and good The inductor is difficult to noise performance. integrate and cost high. Table 2-1 The advantage and disadvantage of different type oscillators. 20.

(34) Some of the most important considerations of VCO are: [2.7]. (1)Phase Stability:. The frequency spectrum of a VCO output should look likes an ideal impulse, i.e., the phase noise of a VCO must be as low as possible.. (2)Electrical Tuning Range:. The tunable frequency range of a VCO must be able to cover the entire required frequency range of the interested application. (3) Tuning Linearity:. An ideal VCO has a constant gain at the entire frequency range. Also, a constant VCO gain can simplifies the design procedure of a VCO.. (4) Power Supply Sensitivity:. Since there are many digital circuits in a modern transceiver circuit, the switching activities of digital circuits will somewhat influence the power supply of the whole system. The switching noise induced by digital circuits will also couple to the power supply of the VCO and influence its output waveform. Therefore, in VCO the dependency of the oscillating frequency on the power supply must be as low as possible.. (5) Frequency pushing:. The dependency of the center frequency on the power supply voltage.. (6) Frequency pulling:. The dependency of the center frequency on the output load impendence. 21.

(35) (7) Low cost, Phase noise, DC consumption current, Harmonic/spurious. gm. V out L. RL. Rc. Rp. Figure 2-12 LC-Tank Voltage-Controlled Oscillator In the next, we will show an LC-Tank VCO, relaxation oscillator and ring oscillator in the Figure 2-12, Figure 2-13 and Figure 2-17. [2.6] In the LC-Tank VCO, the oscillation conditions are already shown by [2.6]. Where RP is the parasitic resistance in parallel to the LC-tank, and RL and RC are the parasitic resistances of L and C, respectively.. ω = 0. 1 LC. Re ff = Rc + RL +. (2.10). 1 RP ⋅ (ω0 C)2. (2.11). Re ff (ω0L)2. (2.12). GM = Re ff (ω0C)2 =. 22.

(36) Figure 2-13 Five stage signal ended ring oscillator. The second type oscillator is ring oscillator as shown in Figure 2-13 has been widely used in PLL for application of clock recovery and clock generation before and Figure 2-14 shows the detail circuit of the Figure 2-13.. A ring oscillator can be smoothly integrated in a standard CMOS process without taking extra processing steps because it dose not require any passive resonant element.. Figure 2-14 Detail five stages circuit in Figure 2-13. 23.

(37) When the ring oscillator is employed as a voltage controlled oscillator, the desired wide operating frequency range can be easily obtained. Different output frequency is achieved by adjusting the timing delay of each stage in the ring oscillator.. Figure 2-15 Differential Ring Oscillator. Also, there is another type of ring oscillator, differential ring oscillator, as shown in Figure 2-15.The detail circuit of Figure 2-15 show in the Figure 2-16.. 24.

(38) Figure 2-16 The circuit of each stage in Figure 2-15. The third type oscillator is the relaxation oscillator, it shows in the Figure 2-17. The relaxation oscillator is also known as multivibrator, incorporating hysteresis characteristics that can oscillate even with a small phase shift. The relaxation oscillator and ring oscillator utilize the positive feedback characteristics and are known as resonatorless oscillators. [2.8]. The other category of oscillator is to eliminate that the real part of the loop’s impedance so that the poles are pure imaginary. The LC-tank VCO is a typical resonator oscillator that bases on the idea and is called resonator oscillator. The VCO is the most challenging part of the PLL and we have to design carefully.. 25.

(39) R1. R2. M1. M2. C1 I. I. Figure 2-17 The relaxation oscillator. 2-3-4 Frequency Divider. In some application, we need a high frequency clock generator and the crystal-oscillator is not satisfied, because the frequency of the crystal-oscillator is too small. Therefore, the multiple-frequency-technology that utilizes PLL is presented. For example, the divider module is four. The output frequency of VCO is a four times of the input reference signal’s frequency, i.e.,. f o u t = N f in. ,. N = 4. (2.13). f out = 4 f in. (2.14). 26.

(40) The Figure 2-18 show an example of divider, it uses a TSPC register. The next is the advantages and the disadvantages of the divider:. Advantages:. Reasonably fast No static power consumption Compact size Differential clock not require. Disadvantages:. Slowed down by stacked PMOS, signals goes through three gates per cycle Requires full swing input clock signal. Figure 2-18 Divide-by-2 using a TSPC register. If we need higher division, it can be achieved by simple cascading divide-by-2 stages.. 27.

(41) The Figure 2-19 shows a divider (1/4) waveform.. Figure 2-19 A divider (1/4) waveform. 2-4 All Digital PLL. Figure 2-20 All Digital Phase-Locked Loop. In this section we will describe All Digital PLL, it has characteristics of fast frequency locking, full digitization and good stability. Because of the availability of low-cost ADPLL ICs, this type of PLL can replace the classical DPLL in many 28.

(42) applications today. The ADPLL is made as a digital building block, it dose not contain any passive component, such as resistors and capacitors.. The ADPLL consists of a digital phase frequency detector (PFD), a control unit, a frequency divider, and digital control oscillator (DCO) as show in Figure 2-20. All signals in the ADPLL are digital signals. The PFD detects the frequency difference and the phase difference between the input reference signal and the feedback signal. The control unit receives the signal, produced by the PFD, and produces a set of digitally controlled signals to control the DCO.. By including a divide-by-N divider in the feedback path, the DCO output frequency runs N times faster than input reference signal. The divided-by-N divider is an optional component in the ADPLL. The functional blocks of the ADPLL imitate the function of the corresponding analog blocks. Because the ADPLL consists of digital circuits entirely, there are many different of design methods to achieve the functions of them.. The ADPLL system is a discrete-time system, hence analyzing the ADPLL in s-domain is not suitable. Although it is possible to take an entire PLL-description and then transform it from s-domain into z-domain, this is unnecessary difficult. Instead, one transforms each component into z-domain and then proceeds with the analysis in z-domain. The ADPLL is best described in z-domain.. In the Linear PLL, Digital PLL and All Digital PLL, they have many advantages and disadvantages respectively. We compare and illustrate them in Table 2-2.As show in the Table 2-2, we can know they use different design methodology, because the 29.

(43) ADPLL is a digital circuit design so it can be designed by standard cell library.. Hence the ADPLL just need a short design cycle. The analog circuits take much time to design, so they take long turnaround time. The ADPLL has higher noise immunity than LPLL and DPLL. The VCO of the LPLL or the DPLL produces a continuous frequency band but the DCO of the ADPLL produces a discrete frequency band, so the VCO has higher resolution than DCO. In general, the digital circuits have lower power consumption than analog circuits. The ADPLL have a less power consumption. Because the loop filter of LPLL or DPLL has one or more large capacitors, whose area can not be efficiently reduced as the process technology improving. In the ADPLL, the area depends on which type of DCO we design and the area of DCO also depends on how many bits we design. The ADPLL shorten lock time by dealing with digital signal. LPLL. DPLL. ADPLL. Design Methodology Analog. Mixed mode. Digital. Design cycle. Slow. Slow. Fast. Noise rejection. Poor. Poor. Good. Output frequency. High. High. Low. Oscillator resolution. High. High. Low. Lock cycle. Slow. Slow. Quick. Power consumption. Large. Large. Small. Area. Large. Large. Design dependent. Table 2-2 The advantage and disadvantage of different type PLL 30.

(44) The design of PLL is a trade-off jitter performance, frequency resolution, phase resolution, lock-in time, area cost, power consumption, circuit complexity and design cycle. It is hard to design one PLL suitable for all applications. For fast-locking frequency synthesizer applications, such as a frequency hopping multiple access system, the lock-in time is the most critical design issue. And for portable or mobile applications, lock-in time is also very important since the PLL must support fast entry and exit from power management techniques.. In traditional analog PLL designs, fast acquisition requires tuning of the VCO free-running frequency near the desired the frequency in advance or to increase loop bandwidth. But increasing the loop bandwidth degrades jitter performance, and the extra VCO tuning range is not easy to be achieved since there always has process variations, voltage variations, and temperate variations (PVT variations). We list some design issues about ADPLL as following table.. Digital Controlled Oscillator The output clock of DCO is discrete, so the resolution of a DCO should be sufficiently high to maintain acceptable jitter. For searching target frequency and phase easily and efficiently, a DCO had better approach a monotonic response to the control word. A DCO had better have high noise immunity, so the output clock will not induce large jitter. Phase Frequency Detector. The resolution of a PFD had better be as high as. 31.

(45) possible. In this way, the PFD can detect tiny phase difference to promote accuracy and to decrease jitter. The PFD had better have two properties simultaneously. One is to judge the modulating direction. The other is to judge the modulating magnitude. Control Unit. Control Unit receives the signal, produced by the PFD, and produces signal to the DCO. It works as a loop filter. It both decides the speed of the lock process and suppresses the high frequency noise to reduce jitter. All responses of an ADPLL are almost decided by this control unit.. Table 2-3 Design issues of ADPLL. 32.

(46) Chapter 3 Proposed Low power Digitally Controlled Oscillator At the heart of the ADPLL is a digitally controlled oscillator because it affects many important specifications of the ADPLL, like maximum operating frequency, operating frequency range and jitter. Like most voltage-controlled oscillators the DCO consists of a frequency-control mechanism within an oscillator block. In this section, we will discuss basic concepts of digitally controlled oscillator, some type of digitally controlled oscillators and the concept of low power digitally controlled oscillator.. 3-1 Basic Concepts of Digitally Controlled Oscillator The fundamental function of a DCO is to provide an output waveform, typically in the form of square wave, which has a frequency of oscillation f. DCO. that is a. function of a digital input word D, as follows:. f DCO = f (D) = f ( dn-1 2n-1 + dn-2 2n-2 +．．．+ d1 21 + d0 20 ). (3.1). Typically, the DCO transfer function f (．．．) is defined so that either the frequency f. DCO. or the period of oscillation TDCO is linear with D, generally with an offset. For. example, a DCO transfer function that is linear in frequency is typically expressed as:. f(D) = f offset + D．Δf. where f. offset is. (3.2). constant offset frequency and Δf is the frequency quantization step. 33.

(47) Similarly, a DCO transfer function that is linear in period is typically expressed as:. T(D) = T offset + D．ΔT. (3.3). Where T offset is constant offset period and ΔT is the period quantization step. It is evident that, since the DCO period T(D) is a function of quantized digital input D, the DCO can not generate a continuous range of frequencies. In this regard, the quantization granularity of the DCO period sets some fundamental limits on the achievable jitter of an all-digital PLL. It is of course desirable to have a fairly small quantization step size (e.g. period quantization step ΔT ). 3-2 Digitally Controlled Oscillator(DCO). An odd number of inverters connected in a circular chain become a ring oscillator. The clock period of the ring oscillator is two times the loop delay time. There are two parameters to modulate the clock period of the ring oscillator. One is the variable propagation delay time of the inverter, and the other is the number of the inverter. Hence, based on tuning these two Parameters with different method, there are many methods to design DCO.. 34.

(48) 1)Variable Propagation Delay Time of the inverter. 10. 10. 10. 10. 9. 9. 9. 9. 10. 10. 10. 10. 9. 9. 9. 9. DCO_control[5]. D C O _control[15:6]. EN A B LE. Figure 3-1 Digitally Controlled Oscillator [3.1]. As show in the Figure 3-1, it is a conventional DCO proposed by Motorola in 1995[3.1]. The ADPLL control the frequency through the DCO control word, the output of the register consisting of some binary weight control signals. The DCO is a ring oscillator with odd inverting stages. There are one enabling NAND gate and eight. 35.

(49) controllable cells in the DCO. In order to provide sufficient DCO control word resolution to maintain acceptable jitter, Motorola also uses several techniques to increase number of the control word. The control devices in a cell have binaryweighted widths, as shown by the constituent cell in Figure 3-2.. DCO N [11] DCO N [12] DCO N [13] DCO N [14] DCO N [15]. M2 OUT. IN M1. D CO [15] D CO [14] D CO [13] D CO [12] D CO [11]. Figure 3-2 The DCO cell [3.1]. 36.

(50) Figure 3-3 Another delay element [3.6]. Fig. 3-3 illustrates another technique for implementing a Variable Propagation Delay Time of inverter. In this circuit, a variable resistor is used to control the delay. A stack n of rows by m columns of nMOS transistors is used to make the variable resistor. This resistor subsequently controls the delay of M1. In the circuit of Fig. 3-3, only the rising edge of the Out can be changed with the input vector. Another stack of pMOS transistors can be used at the source of the pMOS transistor, M2, to have control over the delay of the falling edge.. One of the problems with the above mentioned architectures is the nonmonotonic delay behavior with ascending binary input pattern. As can be seen in the circuits of Figs. 3-2 and 3-3, the input vector changes the effective resistance of transistor(s) placed at the source of the nMOS or pMOS transistors of the first inverter. This not only changes the resistance at the source of or , but also changes the parasitic 37.

(51) capacitance associated with transistors at these nodes. This is because the parasitic capacitance at the drain of a MOSFET is different in the ON and OFF states. Therefore, there are two factors which depend on the input vector and affect the delay[3.6]:. The resistance of the controlling transistor: By increasing/ decreasing the effective ON resistance of the controlling transistor(s) at the source of M1(M2), the circuit delay can be increased/decreased.. The effective parasitic capacitance of the controlling transistor: As the effective capacitance of the controlling transistors at the source of M1(M2) increases due to the input vector, the charge sharing effect causes the capacitance at the output of the current-starved inverter to be (dis)charged faster and the overall delay of the circuit decreases.. The DCO shows in the Figure 3-4[3.4], it describes a possible full-custom implementation of the DCO. A common solution for designing the DCO is to make it as a combination of a D/A converter and VCO. To control the frequency of the VCO, each voltage at node Vn(0) …Vn(6) and Vp(0) …Vp(6) is separately controlled using 14 small D/A converters. So the input of this DCO is also a digital type. To start the VCO at a know state, a pull-down transistor controlled by the signal “Reset” is added. When Reset signal is high, the voltage Vp(6) is set high to prevent a short circuit from occurring.. Figure 3-5 shows the corresponding simulated period time versus digital control word for the D/A –VCO combination [3.4]. Simulated period time versus digital 38.

(52) control word for the D/A converter combination using linear D/A converter is also givens as comparison. Using custom-made D/A converters gives the opportunity to linearize the oscillator by using nonlinear D/A converters. Since the loop gain of the PLL is proportional to UT/T, a completely linear DCO is not the best solution. Instead, effort is made to keep the ratio UT/T constant. To achieve this, a set of control voltage is preliminary calculated. The main source of power consumption for the D/A-VCO is from the D/A converter.. W7. DECODER. 4. D/A. Vn(0). 4. D/A. Vn(6). 4. D/A. Vp(0). 4. D/A. Vp(6). Figure 3-4 (A) DCO consisting of 14 D/A converters and a current-starved inverter VCO [3.4]. 39.

(53) Reset. Vp(0). Vp(1). Vp(2). Vp(6). Vn(0). Vn(1). Vn(2). Vn(6). Figure 3-4 (B)DCO consisting of 14 D/A converters and a current-starved inverter VCO [3.4]. Figure 3-5 Simulated period time versus digital control word W for the DCO of Figure 3-4 [3.4] 40.

(54) Figure 3-6 [3.5] was shown a 4 bits DCO circuit which consists of a D/A converter and an injection-locked oscillator. The main advantages of Figure 3-6 circuit are its simple structure, high resolution and good linearity. The circuit is composed of an injection-locked oscillator (ILO) consisting of MOS transistors M1-M9 and a simple four bits digital controlled current source consisting of MOS transistors M10-M15.. 2/20 2/10 M10 C0. 2/5. 2/2.5. M11 M12 M13 C1. C2. M3. M4. M1. M2. M6. M8. M5. M7. M14. C3 Bias. M15. M9. Figure 3-6 Schematic diagram of a 4 bits DCO [3.5]. In the absence of an input signal, the ILO oscillates at its free running frequency just like a ring oscillator. Its free running frequency is primarily determined by the total propagation delay time of the differential comparator and the inverter chain. The 41.

(55) current output from the D/A is used to bias the differential comparator. Thus, the propagation delay of the comparator is directly proportional to the digital control word.. fout =. D. 1. 1 + D. (3.3) 2. The delay of the comparator is designed to be much larger then the delay of the inverter chain to increase the sensitivity and linearity of the DCO. The output frequency is mainly determined by the sums of two terms, the delays of the comparator and the inverter chain, and these delays can be presented by D1 and D2 respectively. The relation between D1 and D2 was shown in the equation (3.3).. 2) Different number of the inverter. As show in Figure 3-7, it is a multiple path selection DCO with a delay matrix [3.2]. When searching frequency, the path selection works as coarse search and the delay matrix works as fine search. The delay matrix consists of many parallel tri-state inverters. The operating range is determined by number of cascade inverters, and the resolution is decided by scale of delay matrix. Because the standard cells have the problem of accuracy, this multiple path selection DCO uses a parallel structure with matrix encoder to prove accuracy.. 42.

(56) MUX (Coarse Search) Delay Matrix Fine Search. output. Coarse Search command. ENB ENB. Fine Search command. ENB. ENB. Enhanced resolution. Figure 3-7 A multiple path selection DCO [3.2]. RUN. C[0] C[120]. C[1]. C[5]. C[121]. C[125]. Figure 3-8 Numerically controlled oscillator [3.3]. 43.

(57) In Figure 3-8[3.3], it shows a numerically controlled oscillator (NCO) and it is made from standard cells. To change the frequency of the ring oscillator, a set of 21 inverting tri-state gates are connected in parallel with each inverter. When the tri-state gates are enabled additional current drive is added to each inverter stage. The 126 tri-state gates are controlled by a 126 bit vector, C, which is decoded from a 7 bit control word. Although this NCO is made from standard cells, it has relative power consumption, low maximum frequency from high capacitive load in the ring oscillator.. The Figure 3-9 shows the result of the simulation in Figure 3-8. Due to fewer parallel tri-state inverters per stage in the ring oscillator, aside from having evenly distributed clock phases, also performs better both in terms of linearity and maximum clock rate. In Figure 3-10, the DCO consists of path selection with AO gates and delay matrix with several parallel inverters. Its structure is similar to that in Figure 3-7.. Figure 3-9 The simulated period time V.S. digital controlled word in Figure 3-8.. 44.

(58) Figure 3-10 Structure of DCO in [3.7].. Power consumption with above mentioned different number of the inverter is a serious problem. Use more inverters to oscillate the target frequency will result more charging and discharging and it will waste power. In the other word, the technique exchange power for resolution (range). So next section we will introduce my proposed low power DCO.. There are many kinds of digitally controlled oscillators. Different kinds of digitally controlled oscillator have different advantages. There are some issues to design digitally controlled oscillator. First, the output frequency of the DCO is 45.

(59) discrete, so the resolutions of the DCO should be sufficiently high, the sufficiently high resolution to maintain acceptable jitter. Second, the DCO had better approach a monotonic response to the DCO control word. Third, a DCO had better high noise immunity, so the output clock will not induce larger jitter. However, no matter which kinds of oscillator we use, we should check our design conform to these issues or not.. 3-3 Proposed Low Power Digitally controlled Oscillator Last section, we talk about two kinds of digitally controlled oscillator. One is digitally controlled delay time and the other is digitally controlled number of the inverter. If you want to design a low power digitally controlled oscillator, you can` t choose the second type to do. The reason is that the more inverters you use, the more charging and discharging should be resulted. So proposed digitally controlled oscillator will use controlled delay time technique to design.. stage1. stage2 1. stage3 0. stage4 1. stage5 0. 1. Figure 3-11(a) five stages inverter oscillator. In digital aspect, the logic values of both stage1/stage3 output is the same. The signal just passes through stage2 and stage3 with a certain delay time, so we cancel the two inverters (stage2 and stage3) to reduce power. But Changing five stages 46.

(60) inverter for three stages inverter changes delay time (frequency) from long (slow) to short (high), too. If we want that both the delay time (frequency) are the same and power is low, we can use some delay element in three stages inverter oscillator to increase delay time to make the both delay time the same. The most of digitally controlled oscillator use inverter chain to be coarse tune. It makes very much unless charging / discharging nodes and increases uncontrolled intrinsic delay time (like equation 3.3 T offset). Figure 3-7is an example.. VDD. VOUT. VDD. GND. Figure 3-11(b) turn on transmission gate. So, we can find some delay elements just passed signal to be coarse tune circuit. The proposed digitally controlled oscillator use transmission gates to be coarse tune circuit. Choosing transmission gate has three reasons. First, it full swings; doesn’t affect next stage inverter charging/discharging. Second, when inverter charges, the resistance of transmission gate from 0V to 1.2V is almost the same. So we can easily calculate it` s RC delay. In Figure 3-11(b) for low values of Vout, the NMOS device is saturated and the resistance is approximated as:. 47.

(61) Rn =. V DD − Vout = IN. V DD − Vout 2 V DSAT ⎛W ⎞ ⎛ k 'n ⎜ ⎟ ⎜⎜ (V DD − Vout − VTn )V DSAT − 2 ⎝ L ⎠N ⎝ V DD − Vout ≈ k n (V DD − Vout − VTn )V DSAT. ⎞ ⎟⎟ ⎠. (3.4). The resistance goes up for increasing values of Vout, and approaches infinity when Vout reaches VDD-VTn, this is when the device shuts off. Similarly, we can analyze the behavior of the PMOS transistor. When Vout is small, the PMOS is saturated, but it enters the linear mode of operation for Vout approaching VDD. The resistance then approximated by:. Rp =. VDD − Vout = IP. VDD − Vout. 2 ( Vout − VDD ) ⎞ ⎛ W ⎞ ⎛⎜ ⎟ k ' p ⎜ ⎟ ⎜ (− VDD − VTp )(Vout − VDD ) − ⎟ 2 ⎝ L ⎠P ⎝ ⎠ 1 ≈ k p VDD − VTp. (. ). (3.5). The simulated value of Req = Rp || Rn as a function of Vout is plotted in Figure 3-12. It can be observed that Req is relatively constant. The same is true in other design instances (for instance, when discharging CL). When analyzing transmissiongate networks, the simplifying assumption that the switch has a constant resistive value is therefore acceptable.[3.8]. 48.

(62) Figure 3-12 Simulated equivalent resistance of transmission gate for low-to-high transition (for (W/L)n = (W/L)p = 0.5mm/0.25mm).. A similar response for overall resistance is obtained for the high-to-low transition. Next, we calculate the resistance of transmission gate from high to low.. In Figure 3-12 for high values of Vout (high-to-low),the resistance goes up for decreasing values of Vout, and approaches infinity when Vout reaches VDD-|VTp|, this is when the device shuts off. Similarly, we can analyze the behavior of the NMOS transistor. When Vout is high, the NMOS is saturated, but it enters the linear mode of operation for Vout approaching GND. The resistance then approximated by:. 49.

(63) Rn =. Vout = IN. Vout 2 Vout ⎞ ⎛ W ⎞ ⎛⎜ ⎟ k 'n ⎜ ⎟ ⎜ (VDD − VTn )Vout − 2 ⎟⎠ ⎝ L ⎠N ⎝ 1 ≈ k n (VDD − VTn ). (3.6). The PMOS device is saturated and the resistance is approximated as:. Rp =. Vout = IP. (. Vout. ). 2 V DSAT ⎛W ⎞ ⎛ k ' p ⎜ ⎟ ⎜⎜ Vout − VTp V DSAT − 2 ⎝ L ⎠P ⎝ Vout ≈ k p Vout − VTp V DSAT. (. ⎞ ⎟⎟ ⎠. ). (3.7). The Req for high-to-low transition is lower than low-to-high transition. It’s response is like making Figure 3-12 symmetry with y-axis. Next, we will talk about how to make both the same.. If we want the clock of DCO to be duty cycle, we need to make both rising (low-to-high) and falling (high-to-low) the same. According to RC delay equation ( DelayTime = RC ), we should let rising resistance and falling resistance be equal. In Table 3-1, we simulate transmission gate with different size. 50.

(64) Size. Rising(ns). Falling(ns). 0.314. 0.2080. 0.253. 0.2082. 0.216. 0.2083. 0.190. 0.2088. Wp=0.6um Wn=0.2um Wp=0.7um Wn=0.2um Wp=0.8um Wn=0.2um Wp=0.9um Wn=0.2um. Table 3-1 Transmission gate simulation with different size (TSMC 0.13um C=10fF Lp=Ln=0.13um).. According to Table 3-1, when Wp/Wn is almost 4.5 , rising time equals falling time.. Third, according to Table 3-1, we can see that for increasing Wp, it just only influences rising time. In the other word, different width does not affect the driving ability of inverter which drive transmission gate. It only changes equivalent rising/falling resistance. When we choose number of conducting transmission gate, the transmission gate based DCO has monotonic characteristic. So, proposed digitally controlled oscillator (DCO) is based on different number of conducting transmission gate.. 51.

(65) 1.2. 1.2 V1 Vi ․․․. IN 0. C. 1.2. 1.2. Vi-1. C. 0. Vi. C. 0. 1.2 Vi+1 Vn-1 ․․․. C. 0. C. C. Vn. 0. C. Figure 3-13 (a) A chain of transmission gates. Req IN. Req V1 Vi ․․․ C. Req Vi-1. C. Req Vi. C. Req Vi+1 Vn-1 ․․․. C. C. Vn. C. C. Figure 3-13 (b) Equivalent RC network. Now, we talk about the delay time of a chain transmission gate. Figure 3-13 (a) shows a chain of n transmission gates. Figure 3-13 (b) shows the transmission gate replaced by equivalent resistance. The exact analysis of delay is not simple, but as discussed earlier, we can estimate the dominant time constant at the output of a chain of n transmission gates as follows:. τ ( Vn ) =. n. ∑. k =0. CR. eq. k = CR. 52. eq. n ( n + 1) 2. (3.8).

(66) Equation 3.8 means that the delay time is proportional to n2 and increase rapidly with the number of transmission gates. Proposed DCO architecture is two step, coarse tune and fine tune. If the difference of coarse tune cell delay time between each step is too big, the overall fine tune cell number must be more. Overall fine tune cell delay time increases and overall fine tune cell area increases, too. Choosing appropriate cascade transmission gate number is more important. So, in my proposed digitally controlled oscillator, we choose two-bit controlled signal and have four different number of transmission gate. According to table 3-1, we choose Wp=0.9um, Wn=0.2um. We proposed two architectures below and we will discuss them.. A. ․. Match SN1. ․ S1 SN2. ․ S2 SN3. S3 SN4. S3. S4. S2. ․ B. ․. ․ D. ․ C SN2. SN3. S4. ․ E. Fine Tune Cell. SN4. Figure 3-14 (a) Type-1 DCO. S1 Match. SN1. S2. ․ A S1. SN2. ․ B S2. S3. SN3. ․ C. S4. ․. E. ․ D SN4. S3. Figure 3-14 (b) Type-2 DCO. 53. Fine Tune Cell.

(67) As increasing number of series transmission gate, we get delay time, CReq 3CReq 6 CReq 10 CReq․․․. Because delay time increase rapidly, we choose four transmission gate to design. In Figure 3-14, shows two proposed Type-1 and Type-2 DCO. Both Type-1 and Type-2 are controlled by two bits. Next, we will talk about the difference between them.. In Figure 3-14 (a), node A capacitance is bigger than B, C, D and E. In Figure 3-15 (b), node E is bigger than A, B, C, and D. In Figure 3-14, we can see that the charging/discharging resistance between Type-1 node A and Type-2 node E is not the same. Type-1 node A resistance is the output of last inverter. If we choose path 4 open (signal pass through A, B, C, D and E), Type-1 node A resistance is the output of last inverter and Type-2 node E resistance is the output of last inverter and 4 Req (transmission gate resistance). The difference will make Type-2 intrinsic delay time big. The big intrinsic delay time will make the DCO frequency slow. So, if we want high speed, we should choose type-1 DCO.. Above, we talked about that as increasing number of series transmission gate, delay time increase rapidly. Now we introduce the tip we reduce the amount of increasing. First, we let two transmission gates be shunt. Figure 3-15 shows the architecture of Type-1 shunt transmission gate and it` s equivalent circuit. Figure 3-16 shows the architecture of Type-2 shunt transmission gate and it` s equivalent circuit.. 54.

(68) ․. Match. A. ․. SN1. ․. S2. S1. ․. SN3. SN2. S3. S4. SN4 S4. ․ B. SN2 S2. ․ C. ․ D. SN3. ․ E. Fine Tune Cell. SN4. S3. Figure 3-15 (a) Type-1 shunt transmission gate. Req A. E. IN 2C. Figure 3-15 (b) Path 1 (AE) equivalent circuit. Req/2. Req. A. D. E. IN 2C. 6C. Figure 3-15 (c) Path 2 (ADE) equivalent circuit. Req/2 A. Req/2 C. Req D. E. IN 6C. 6C. Figure 3-15 (d) Path 3 (ACDE) equivalent circuit. 55. 2C.

(69) Req/2. Req/2. A. Req. Req/2. B. C. D. E. IN 6C. 4C. 6C. 2C. Figure 3-15 (e) Path 4 (ABCDE) equivalent circuit. Equation (3.9) is Figure 3-15(b) in mathematics. τ p1 = Re q * 2C. (3.9). Equation (3.10) is Figure 3-15(c) in mathematics. 1 2. 3 2. τ p 2 = ( Re q ) * 6 C + ( Re q ) * 2 C =τ. p1. 1 ⎛1 ⎞ + Re q * 6 C + ⎜ Re q * 2 C ⎟ 2 ⎝2 ⎠. (3.10). Equation (3.11) is Figure 3-15(d) in mathematics. 1 2. τ p 3 = ( Re q) * 6C + (Re q) * 6C + (2 Re q) * 2C =τ p2. (3.11). ⎛1 ⎞ + Re q * 6C + ⎜ Re q * 2C ⎟ ⎝2 ⎠. 56.

(70) Equation (3.12) is Figure 3-15(e) in mathematics. 1 2. 3 2. 5 2. τ p 4 = ( Re q) * 4C + (Re q) * 6C + ( Re q) * 6C + ( Re q) * 2C = τ p3. (3.12). 3 ⎛1 ⎞ + Re q * 6C + ⎜ Re q * 2C ⎟ 2 ⎝2 ⎠. S1 Match. SN1 A. ․. S1. S2. ․ SN2 B. S2. ․. S3. E. ․ SN3 C. S3. S4. ․ D SN4. Figure 3-16 (a) Type-2 shunt transmission gate. Req A. E. IN 4C. Figure 3-16 (b) Path 1 (CE) equivalent circuit. 57. Fine Tune Cell.

(71) Req/2. Req. A. B. E. IN 4C. 5C. Figure 3-16 (c) Path 2 (CDE) equivalent circuit. Req/2. Req/2. A. B. Req C. E. IN 5C. 5C. C. Figure 3-16 (d) Path 3 (BCDE) equivalent circuit. Req/2 A. Req/2. Req. Req/2. B. C. D. E. IN 5C. 5C. 5C. 4C. Figure 3-16 (e) Path 4 (ABCDE) equivalent circuit. Equation (3.13) is Figure 3-16(b) in mathematics. τ p1 = (Re q) * 4C. (3.13) 58.

(72) Equation (3.14) is Figure 3-16(c) in mathematics. 1 2. 3 2. τ p 2 = ( Re q) * 5C + ( Re q) * 4C (3.14). 1 ⎛1 ⎞ = τ p1 + Re q * 5C + ⎜ Re q * 4C ⎟ 2 ⎝2 ⎠. Equation (3.15) is Figure 3-16(d) in mathematics. 1 2. τ p 3 = ( Re q) * 5C + (Re q) * 5C + (2 Re q) * 4C =τ p2. (3.15). ⎛1 ⎞ + Re q * 5C + ⎜ Re q * 4C ⎟ ⎝2 ⎠. Equation (3.16) is Figure 3-16(e) in mathematics. 1 2. 3 2. 5 2. τ p 4 = ( Re q ) * 5C + (Re q) * 5C + ( Re q) * 5C + ( Re q) * 4C = τ p3. 3 ⎛1 ⎞ + Re q * 5C + ⎜ Re q * 4C ⎟ 2 ⎝2 ⎠. 59. (3.16).

(73) Now, we list a table to show the different by changing delay path.. Type-1. With shunt. Without shunt. Path 1 to Path 2. 3 Re qC + (Re qC ). 3 Re qC + (2 Re qC ). Path 2 to Path 3. 6 Re qC + (Re qC ). 6 Re qC + (2 Re qC ). Path 3 to Path 4. 9 Re qC + (Re qC ). 9 Re qC + (2 Re qC ). Table 3-2 the increment of Type-1 with and without shunt. Type-2. With shunt. Without shunt. Path 1 to Path 2. 5 Re qC + (2 Re qC ) 2. 3 Re qC + (4 Re qC ). Path 2 to Path 3. 5 Re qC + (2 Re qC ). 6 Re qC + (4 Re qC ). Path 3 to Path 4. 15 Re qC + (2 Re qC ) 2. 9 Re qC + (4 Re qC ). Table 3-3 the increment of Type-2 with and without shunt. Compare Table 3-2 with Table 3-3, we can see that the Type-1 increment is not better than Type-2. In Table 3-3, the increment gets closer and gets smaller. If we let more transmission gates shunt, the difference is smaller. So we change Type-2 to shunt and don’t change Type-1.. 60.