Chapter 4 Hardware Implementation
4.4 Complexity and Performance
4.4.2 Realistic Performance
Generating Channel Coefficients
As the works shown in section 4.3.2, we implement a circuit which can yield channel coefficients at the rate of 12.5M per second each path for a 6 –ray fast fading channels, which is largely beyond the system’s need. And this channel coefficients generator can be used for other fast fading channel simulation as well.
In this chapter, we introduced the system hardware implementation. Three triangular functions are compared and discussed. And we think LUTs is more suitable for channel simulator implementation, since it needs no multiplier and fast.
Two single-ray Rayleigh fading channel simulators are also implemented with different triangular function algorithms. Both channel simulators can yield more than 100 M channel coefficients per second. Jakes model is less complex, Xiao model has good statistical properties. So, it depends on the limitation of hardware. In a smaller chip, Jakes model is more suitable, while in a lager chip, Xiao model is the one we recommend.
Finally, a 6-ray fading channel simulator is made. The one implemented by LUTs is recommend, it can generate 12.5M channel coefficients per second each path.
Chapter 5 Conclusion
FPGA is a very powerful hardware for implementing the digital signal processing circuits. The programmable property for FPGA makes it flexible to different kind of circuits, we can implement the circuits for specific uses, design and optimize the circuit with its specialty. Just as we used a simplified LUTs with not much precision, and it is satisfactory for implementing our channel simulator, since the coefficients are statistical characterized.
We first introduced an OFDM-based system, IEEE 802.16a, including the background, OFDM basic ideas, and the specification. We also defined several parameters and picked a suitable channel model for our channel simulation. The possible mobility supporting rate limitation is discussed as well. The structure of the DSP-FPGA embedded card—Quixote-III— and the chip introduction were then given. Implementation considerations of our works and the performance of the simulator are explained. Three triangular function generator algorithms, two single-ray channel models and a 6-ray Rayleigh fading channel were discussed and compared.
An FPGA structured channel simulator was implemented finally. It can emulate a 6-ray Rayleigh fading channels environment and yield 12.5 M channel coefficients per second.
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作者簡歷
余子瀚，男，一九七九年出生於台灣省屏東。二零零二年畢業於國立交通大學電 子工程學系。同年九月，升入國立交通大學電子研究所碩士班，在通訊電子與訊 號處理實驗室中從事無線通訊相關領域之研究。二零零四年六月取得碩士學位，
論文題目為“可程式化閘陣列之快速瑞立衰褪通道模擬器 ”。研究範圍和興趣包 括 : 無線通道模擬、通道估測、行銷管理等。